DM I_TXP_3
DM I_TXN _2
DM I_TXP_2
DM I_TXN _3
DM I_TXP_0
DM I_TXN _0
DM I_TXN _1
DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1
H_AZ I L_ SD O
BRE F_ REXT
DAC _ RED
DAC _ GR EEN
H_AZ I L_ SY NC
DAC _ BL UE
C14
22p_50V_N PO_04
C20 1U_6.3V_X5R _04
R38 *0_04
CEDARVIEW
DMI
1 O F 6
R EV = 1.10
U12 A
CD V_ 2 2 MM _R EV1P1 0 _ 5
DMI_REFCLKP
N9
DMI_REFCLKN
N8
DMI_REF1P5
T2
DMI_RXN3
P3
DMI_RXP3
P2
DMI_RXN2
N1
DMI_RXP2
N2
DMI_RXN1
M2
DMI_RXP1
M3
DMI_RXN0
L2
DMI_RXP0
L3
DM I_ RC OM P
T1
RS VD_TP_R7
R7
RS VD_TP_R8
R8
DMI_TXN3
N6
DM I_TXP3
N5
DMI_TXN2
L8
DM I_TXP2
L9
DMI_TXN1
L6
DM I_TXP1
L5
DMI_TXN0
K5
DM I_TXP0
K6
C237 0.1u_10V_X7R _04
R209 7.5K_1%_04
R40 *0_04
C236 0.1u_10V_X7R _04
C256
1u_6.3V _X5R _04
R 45 33_04
R21
7.5K_1%_04
R193 150_1% _04
C240 0.1u_10V_X7R _04
R17 2.2 K_0 4
R192 150_1% _04
X5
FSX8L_27MH z
1 2
DM I_TXP_1
IHDA
DD I
CED ARVIEW
LVDS
VGA
3 OF 6
REV = 1.10
U12 C
CD V_ 22M M_ R EV1P1 0_5
DPL_REFCLKP
B9
DP L_ R EFC LK N
A9
AZIL_ R ST#
E21
AZIL_ SD O
F21
AZIL_ SD I
E22
AZIL_ SY NC
F22
AZIL_ BC LK
H21
BR EFR EXT
F15
BR EF1 P5V
E15
RS VD_TP_ H17
H17
RS VD_TP_ J 17
J17
DD I1_ T XN 3
K13
DD I1_ T XP3
J13
DD I1_ T XN 2
E13
DD I1_ T XP2
F13
DD I1_ T XN 1
H11
DD I1_ T XP1
J11
DD I1_ T XN 0
F11
DD I1_ T XP0
E11
DD I1_ HPD
D26
DD I1_ AUXN
C10
DD I1_ AUXP
D10
DD I1_DD C_SD A
G27
DD I1_DD C_SC L
F25
RS VD_TP_ J 15
J15
RS VD_TP_ H15
H15
DD I0_ T XN 3
A7
DD I0_ T XP3
B7
DD I0_ T XN 2
C3
DD I0_ T XP2
D4
DD I0_ T XN 1
F2
DD I0_ T XP1
F3
DD I0_ T XN 0
G3
DD I0_ T XP0
G2
DD I0_ HPD
H22
DD I0_ AUXN
B8
DD I0_ AUXP
C8
DD I0_DD C_SD A
J22
DD I0_DD C_SC L
H25
PANE L_VD DE N
F29
PAN EL_ BKL TE N
E25
P ANEL_ BKL TC TL
G2 2
LV D S _ C LK N
J4
LVDS_C LKP
H4
LVDS_TXN3
G6
LVD S_TXP3
G5
LVDS_TXN2
H8
LVD S_TXP2
H7
LVDS_TXN1
E8
LVD S_TXP1
F8
LVDS_TXN0
H1 0
LVD S_TXP0
G1 0
LVDS _VR EFL
H3
LVDS_VREF H
H2
LVDS_VB G
F10
LVDS _IB G
E10
LV DS_ D DC _D ATA
H2 4
LVDS_D DC _ CL K
G2 4
LV DS_C TR L_D ATA
E24
LVDS_C TRL_CLK
F28
DPL_REFSSCCLK N
E17
D PL_REF SSCC LKP
F17
CR T_ D DC _ CL K
E27
CRT_DDC_DATA
E29
CR T_ IR EF
A13
CR T_ IR T N
D1 2
CR T_B LU E
C1 1
CR T_ G REE N
B11
CRT_RED
B12
CR T_ VS YN C
C1 4
CRT_HSYNC
D1 4
R191 150_1% _04
C238 0.1u_10V_X7R _04
C243 *0.1u_10V_X7R_04
R 48 90.9_1%_04
HDMIC_C1CN
HDMIC_C1CP
HDMIC_C2CP
HDMIC_CLKCP
HDMIC_CLKCN
HDMIC_C0CN
HDMIC_C0CP
HDMIC_C2CN
L47 *H CB1005K F-121T20_short
R26 * 10 K_ 0 4
R20
2.2K_04
R4
1M_04
C13
22p_50V_N PO_04
C242 *0.1u_10V_X7R_04
R39 *0_04
T1
R19
10K_04
R199 619_1% _04
R 44 90.9_1%_04
R24 2.37K_1%_04
C248 *0.1u_10V_X7R_04
R18
10K_04
R 47 90.9_1%_04
R16 2.2 K_0 4
D0 3
R41 *0_04
C249 *0.1u_10V_X7R_04
R 49 90.9_1%_04
3.3VS
1.5VS
3.3V S
1.5VS_DM IREF
1. 5 V S
C LK_D R EFSS# 7
DAC_GREEN 13
CLK_DREFSS 7
DAC_HSYNC 13
DAC_BLUE 13
DAC_VSYNC 13
DAC_DDCACLK 13
DAC_RED 13
DAC_DDCADATA 13
D MI_ IC H_ IT_MR 1 _D N8
D MI_ IC H_ IT_MR 0 _D P8
D MI_ IC H_ IT_MR 1 _D P8
D MI_ IC H_ IT_MR 0 _D N8 DMI_ICH_MT_IR0_DN 8
DMI_ICH_MT_IR0_DP 8
DMI_ICH_MT_IR1_DP 8
DMI_ICH_MT_IR1_DN 8
AZ_SDIN110
3.3VS6,7, 8,9,10,11,12,13,14,15, 16,21
AZ_SY NC10,14
AZ_BITC LK10 , 1 4
AZ_SDOUT10,14
L_DDC_DATA 12
AZ_R ST#10 , 1 4
LVDS -L2P 12
LVDS-L2N 12
LVDS-L1N 12
MC H_ B L O N 1 2
LVDS-LCLKP 12
D DI1 D ISABL E: 2.2K TO GN D
LV D D _E N 1 2
LVDS -L1P 12
L_ DD C_ C LK 12
LVDS- LC LKN 12
LVDS -L0P 12
1.5VS5,7,8, 11,21
LVDS-L0N 12
CLK_CPU_DMI#7
HDMI_CTRLCLK16
CLK_CPU_DMI7
HD MI_ C TRL DA TA16
HD MIC _ CL KC P16
POR TC_HP C16
R15
*HC B1005K F-121T20_short
HD MI C_ C1 C P16
HDMIC_CLKCN16
HDMIC_C1CN16
HDMIC_C2CN16
HD MI C_ C2 C P16
HD MI C_ C0 C P16
D MI_ IC H_ IT_MR 2 _D P8
HDMIC_C0CN16
D MI_ IC H_ IT_MR 2 _D N8
D MI_ IC H_ IT_MR 3 _D N8
D MI_ IC H_ IT_MR 3 _D P8 DMI_ICH_MT_IR3_DP 8
DMI_ICH_MT_IR2_DN 8
DMI_ICH_MT_IR2_DP 8
DMI_ICH_MT_IR3_DN 8
R23 *10m il_short
R22 *10m il_short
VGA RGB r e sis to rs co ls e t o MCH b all
Zo = 37.5 Ohm ? 5%
sig na l : 9 mils
length < 800 mils
Two VGA RGB resistors between
Zo = 50 Oh m ? 5%
sig na l : 5 mils
len gt h < 14000 mils
LVD_V REFL_O UT_R
LVD_VREFH_OUT_R
LVD_I BG
DPL_REFCLKP
DMI_RCOMP
OPTION
D03
Zdiff = 90 Ohm ? 0%
signal / space : 4 / 5 mils
le ng th < 785 0 mils
(1)
(2 )
LVDS Control Signal Group
LBKLT_CTL ,LBKLT_EN,LVDD_EN
(1)
LVDS Clock & Da ta Signal Group
Zo = 50 Ohm ? 0%
si gn al : 5 mils
le ng th < 6000 mils
LVD _V REFH _OU T_R
TP_LVD_VB G
LVD _I BG
LVD _V REFL_O UT_R
LCTLA_CLK
LVD S_BKLTCTL
LCTLB_DATA
H_AZ I L_ SD I
DAC_BLUE
DAC_GREEN
DAC_RED
DMI_RCOMP
length < 500mils
DPL_REFCLKN
LCTLB_D ATA
Z diff = 80 Ohm ? 7.5%
l en gt h =b r eak ou t( <=50 0mils) +(< = 6000 mils)
DM I Signal Group
BRE F_ 1P 5V
DAC REF SET
LCTLA_C LK
DD I_DD C_SD A
H_AZ I L_ BC LK
LA Y O UT NOT E:
Place VGA RGB resistors close to MCH
< 800 mils t o M CH ball
D0 3
H_AZ I L_ R ST#
DMI_RXN_3
DMI_RXP_2
DMI_RXN_2
DMI_RXP_3
(1)
(2)
3/7
(3)
(2)
CRT Sync Signal Group
DAC_HSYNC,DAC_VSYNC
Zo = 50 Ohm ? 5%
sig na l : 5 mils
len gth < 14500 mils
(1)
CRT DAC Sign al Grou p
CRT_RED,CRT_GREEN, CRT_BLUE
(3)
CRT Control Signal Group
CRT_DDC_CLK,CRT_DDC_DATA
Zo = 50 Oh m ? 5%
sig nal : 5 mils
len gt h < 15100 mil s
D ACR EFSE T
LA Y O UT NOT E:
Pla ce DA C REF SET r e s i st or c lo s e t o M C H
< 500 mils t o M CH ball
PORTC_HPC
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