GR712RC-QSG
November 2018, Version 1.0
13 www.cobham.com/gaisler
Clock gating unit
0x80000d00 Unlock register 0x00000000
0x80000d04 Clock enable register 0x00000007
0x80000d08 Reset register 0x00000ff8
AHB Status Register
0x80000f00 Status register 0x00000012
0x80000f04 Failing address register 0x80000f04
Generic UART
0x80100104 UART Status register 0x00000086
0x80100108 UART Control register 0x80000003
0x8010010c UART Scaler register 0x0000009b
Generic UART
0x80100204 UART Status register 0x00000086
0x80100208 UART Control register 0x80000003
0x8010020c UART Scaler register 0x0000009b
Generic UART
0x80100304 UART Status register 0x00000086
0x80100308 UART Control register 0x80000003
0x8010030c UART Scaler register 0x0000009b
Generic UART
0x80100404 UART Status register 0x00000086
0x80100408 UART Control register 0x80000003
0x8010040c UART Scaler register 0x0000009b
Generic UART
0x80100504 UART Status register 0x00000086
0x80100508 UART Control register 0x80000003
0x8010050c UART Scaler register 0x0000009b
Timer Unit with Latches
0x80100600 Scalar value register 0x0000002f
0x80100604 Scalar reload value register 0x0000002f
0x80100608 Configuration register 0x0000003a
0x8010060c Latch configuration register 0x00000000
0x80100610 Timer 0 Value register 0xffffffff
0x80100614 Timer 0 Reload value register 0xffffffff
0x80100618 Timer 0 Control register 0x00000043
0x8010061c Timer 0 Latch register 0x00000000
0x80100620 Timer 1 Value register 0xa0080048
0x80100624 Timer 1 Reload value register 0xa0080048
0x80100628 Timer 1 Control register 0x00000040
0x8010062c Timer 1 Latch register 0x00000000
One can limit the output to certain cores by specifying the core(s) name(s) to the info sys and info reg commands.
As seen below the memory parameters, first UART and first Timer core information is listed.
grmon2> info sys mctrl0
mctrl0 Aeroflex Gaisler Memory controller with EDAC
AHB: 00000000 - 20000000
AHB: 20000000 - 40000000
AHB: 40000000 - 80000000
APB: 80000000 - 80000100
8-bit prom @ 0x00000000
32-bit static ram: 1 * 8192 kbyte @ 0x40000000
32-bit sdram: 2 * 128 Mbyte @ 0x60000000
col 10, cas 2, ref 7.8 us
grmon2> info sys uart0 gptimer0
uart0 Aeroflex Gaisler Generic UART
APB: 80000100 - 80000200
IRQ: 2
Baudrate 38461
gptimer0 Aeroflex Gaisler Modular Timer Unit
APB: 80000300 - 80000400
IRQ: 8
16-bit scalar, 4 * 32-bit timers, divisor 80
The GR712RC has a clock-gating unit which can disable and enable clock gating and generate reset signals of
certain cores in the SOC. With the GRMON grcg command the current setting of the clock-gating unit can be
inspected and changed, the command line switch -cginit also affects the clock-gating unit. See [RD-4] for
more information. Below is an example where the GRETH Ethernet core's clocks are turned on (not gated).
grmon2> grcg
GRCLKGATE GR712RC info:
Unlock register: 0x00000000
Clock enable register: 0x00000006
Reset register: 0x00000ff9
GR712RC decode of values:
+------+----------+----------------------------+----------+---------+-------+
| Gate | Core(s) | Description | Unlocked | Enabled | Reset |
+------+----------+----------------------------+----------+---------+-------+
| 0 | GRETH | 10/100 Ethernet MAC | 0 | 0 | 1 |