COBHAM GRMON3 - Page 152

GRMON3-UM
June 2019, Version 3.1.0
152 www.cobham.com/gaisler
l2cache split boolean
Enable or disable AHB SPLIT response support for the L2 cache controller.
RETURN VALUE
Upon successful completion l2cache lookup returns a list of addr, way, tag, index, offset, valid bit, dirty bit and
LRU bit.
Commands l2cache show data and l2cache show tags returns a list of entries. For data each entry contains an
address and 8 data words. The entry for tag contains index, address, LRU and list of valid bit, dirty bit and tag
for each way.
Upon successful completion l2cache ft, l2cache hprot, l2cache smode and l2cache wt returns a boolean.
Command l2cache hit returns hit-rate and front bus usage-rate.
Command l2cache status returns control and status register values.
Upon successful completion l2cache dcb and l2cache tcb return check bits for data or tags.
Command l2cache mtrr returns a list of values.
SEE ALSO
Section 3.4.15, “CPU cache support”