COBHAM GRMON3 - USB Host Controller; Switches; Commands; I 2 C

GRMON3-UM
June 2019, Version 3.1.0
67 www.cobham.com/gaisler
IRQ: 13
cnt-pwm: 3
The GRPWM core is accessed using the command grpwm, see command description in Appendix B, Command
syntax for more information.
6.6. USB Host Controller
The GRUSBHC host controller consists of two host controller types. GRMON provides a debug driver for each
type. The info sys command displays the number of ports and the register setting for the enhanced host controller
or the universal host controller:
usbehci0 Cobham Gaisler USB Enhanced Host Controller
AHB Master 4
APB: C0100300 - C0100400
IRQ: 6
2 ports, byte swapped registers
usbuhci0 Cobham Gaisler USB Universal Host Controller
AHB Master 5
AHB: FFF00200 - FFF00300
IRQ: 7
2 ports, byte swapped registers
If more than one ECHI or UCHI core exists in the system, it is possible to specify which core the internal commands
should operate on. This is achieved by appending a device name parameter to the command. The device name is
formatted as usbehci#/usbuhci# where the # is the device index. If the device name is omitted, the command
will operate on the first device. The device name is listed in the info sys information.
6.6.1. Switches
-nousbrst
Prevent GRMON from automatically resetting the USB host controller cores.
6.6.2. Commands
The drivers for the USB host controller cores provides the commands listed in Table 6.3.
Table 6.3. GRUSBHC commands
ehci Controll the USB host ECHI core
uhci Controll the USB host UHCI core
6.7. I
2
C
The I
2
C-master debug driver initializes the core’s prescaler register for operation in normal mode (100 kb/s). The
driver supplies commands that allow read and write transactions on the I
2
C-bus. I.a. it automatically enables the
core when a read or write command is issued.
The I2CMST core is accessed using the command i2c, see command description in Appendix B, Command syntax
for more information.
6.8. I/O Memory Management Unit
The debug driver for GRIOMMU provides commands for configuring the core, reading core status information,
diagnostic cache accesses and error injection to the core’s internal cache (if implemented). The debug driver also
has support for building, modifying and decoding Access Protection Vectors and page table structures located in
system memory.
The GRIOMMU core is accessed using the command iommu, see command description in Appendix B, Command
syntax for more information.
The info sys command displays information about available protection modes and cache configuration.
iommu0 Cobham Gaisler IO Memory Management Unit