COBHAM GRMON3 - Page 228

GRMON3-UM
June 2019, Version 3.1.0
228 www.cobham.com/gaisler
<devname#>
1
::vendor
<devname#>
1
::device
<devname#>
1
::command
<devname#>
1
::status
<devname#>
1
::revision
<devname#>
1
::ccode
<devname#>
1
::csize
<devname#>
1
::tlat
<devname#>
1
::htype
<devname#>
1
::bist
<devname#>
1
::bar0
<devname#>
1
::bar1
<devname#>
1
::bar2
<devname#>
1
::bar3
<devname#>
1
::bar4
<devname#>
1
::bar5
<devname#>
1
::cardbus
<devname#>
1
::subven
<devname#>
1
::subdev
<devname#>
1
::rombar
<devname#>
1
::pri
<devname#>
1
::sec
<devname#>
1
::sord
<devname#>
1
::sec_tlat
<devname#>
1
::io_base
<devname#>
1
::io_lim
<devname#>
1
::secsts
<devname#>
1
::memio_base
<devname#>
1
::memio_lim
<devname#>
1
::mem_base
<devname#>
1
::mem_lim
<devname#>
1
::mem_base_up
<devname#>
1
::mem_lim_up
<devname#>
1
::io_base_up
<devname#>
1
::io_lim_up
<devname#>
1
::capptr
<devname#>
1
::res0
<devname#>
1
::res1
<devname#>
1
::rombar
<devname#>
1
::iline
<devname#>
1
::ipin
<devname#>
1
::min_gnt
<devname#>
1
::max_lat
<devname#>
1
::bridge_ctrl
If the PCI bus has been registered into the GRMON's device handling system the PCI Plug and Play con-
figuration space registers will be accessible from the Tcl variables listed above. Depending on the PCI
header layout (standard or bridge) some of the variables list will not be available. Some of the read-only
registers such as DEVICE and VENDOR are stored in GRMON's memory, accessing such variables will
not generate PCI configuration accesses.
<devname#>
1
::<regname>
2
<devname#>
1
::<regname>
2
::<fldname>
3
Many devices exposes their registers, and register fields, as variables. When writing these variables, the
registers on the target system will also be written.
grmon3> info sys
...
2
Replace with a register name
3
Replace with a register field name