Cypress MB95710M Series - Page 130

MB95710M Series
MB95770M Series
Document Number: 002-09307 Rev. *D Page 129 of 172
SPL: Pin state setting bit in the standby control register (STBC:SPL)
Hi-Z: High impedance
*1: PF0/X0 and PF1/X1 transit to this state on a reset when configured as a main clock oscillation pins.
*2: The pin stays at the state shown when configured as a general-purpose I/O port.
*3: “Input blocked” means direct input gate operation from the pin is disabled.
*4: “Input enabled” means that the input function is enabled. While the input function is enabled, execute a pull-up op-
eration or a pull-down operation to prevent leaks due to external input. If a pin is used as an output port, its pin state
is the same as that of other ports.
*5: The PF2/RST
pin stays at the state shown when configured as a reset pin.
*6: PG1/X0A and PG2/X1A transit to this state on a reset when configured as subclock oscillation pins.
*7: The pull-up control setting is still effective.
*8: The MB95710M Series and the MB95770M Series have different SEG output assignment as shown below.
Pin name
Normal
operation
Sleep mode
Stop mode Watch mode
On reset
SPL=0 SPL=1 SPL=0 SPL=1
PE0/
SEG14*
8
/
SEG22*
8
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*
3
-Hi-Z
- Input blocked*
3
- Previous state
kept
- Input blocked*
3
-Hi-Z
- Input blocked*
3
-Hi-Z
- Input blocked*
3
PE1/
SEG15*
8
/
SEG23*
8
PE2/
SEG16*
8
/
SEG24*
8
PE3/
SEG17*
8
/
SEG25*
8
PE4/
SEG18*
8
/
SEG26*
8
PE5/
SEG19*
8
/
SEG27*
8
/
TO11
PE6/
SEG20*
8
/
SEG28*
8
/
TO10
PE7/
SEG21*
8
/
SEG29*
8
/
EC1
SEG output Pin on MB95710M Series Pin on MB95770M Series
SEG06 PC4 P60
SEG07 PC5 P61
SEG08 PC6 P62
SEG09 PC7 P63
SEG10 P60 P64
SEG11 P61 P65
SEG12 P62 P66
SEG13 P63 P67
SEG14 P64 PE0
SEG15 P65 PE1
SEG16 P66 PE2