Cypress MB95710M Series - Page 144

MB95710M Series
MB95770M Series
Document Number: 002-09307 Rev. *D Page 143 of 172
22.4.2 Source Clock/Machine Clock
(VCC = 1.8 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter Symbol
Pin
name
Value
Unit Remarks
Min Typ Max
Source clock
cycle time*
1
tSCLK —
61.5 — 2000 ns
When the main external clock is used
Min: F
CH = 32.5 MHz, divided by 2
Max: F
CH = 1 MHz, divided by 2
— 250 — ns When the main CR clock is used
62.5 — 250 ns
When the main PLL clock is used
Min: F
CH = 4 MHz, multiplied by 4
Max: F
CH = 4 MHz, no division
62.5 — 250 ns
When the main CR PLL clock is used
Min: F
CRH = 4 MHz, multiplied by 4
Max: F
CRH = 4 MHz, no division
—61—µs
When the sub-oscillation clock is used
F
CL = 32.768 kHz, divided by 2
—20—µs
When the sub-CR clock is used
F
CL = 100 kHz, divided by 2
Source clock
frequency
F
SP
—
0.5 — 16.25 MHz When the main oscillation clock is used
— 4 — MHz When the main CR clock is used
8 — 16 MHz When the main PLL clock is used
8 — 16 MHz When the main CR PLL clock is used
F
SPL
— 16.384 — kHz When the sub-oscillation clock is used
— 50 — kHz
When the sub-CR clock is used
F
CRL = 100 kHz, divided by 2
Machine clock
cycle time*
2
(minimum
instruction
execution time)
tMCLK —
61.5 — 32000 ns
When the main oscillation clock is used
Min: F
SP = 16.25 MHz, no division
Max: F
SP = 0.5 MHz, divided by 16
250 — 4000 ns
When the main CR clock is used
Min: F
SP = 4 MHz, no division
Max: F
SP = 4 MHz, divided by 16
62.5 — 2000 ns
When the main PLL clock is used
Min: F
SP = 4 MHz, multiplied by 4
Max: F
SP = 4 MHz, divided by 16
62.5 — 2000 ns
When the main CR PLL clock is used
Min: F
SP = 4 MHz, multiplied by 4
Max: F
SP = 4 MHz, divided by 16
61 — 976.5 µs
When the sub-oscillation clock is used
Min: F
SPL = 16.384 kHz, no division
Max: F
SPL = 16.384 kHz, divided by 16
20 — 320 µs
When the sub-CR clock is used
Min: F
SPL = 50 kHz, no division
Max: F
SPL = 50 kHz, divided by 16