Cypress MB95710M Series - Page 145

MB95710M Series
MB95770M Series
Document Number: 002-09307 Rev. *D Page 144 of 172
(VCC = 1.8 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
*1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio select bits
(SYCC:DIV[1:0]). This source clock is divided to become a machine clock according to the division ratio set by the
machine clock division ratio select bits (SYCC:DIV[1:0]). In addition, a source clock can be selected from the follow-
ing.
• Main clock divided by 2
• PLL multiplication of main clock (Select a multiplication rate from 2, 2.5, 3 and 4.)
• Main CR clock
• PLL multiplication of main CR clock (Select a multiplication rate from 2, 2.5, 3 and 4.)
• Subclock divided by 2
• Sub-CR clock divided by 2
*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
Parameter Symbol
Pin
name
Value
Unit Remarks
Min Typ Max
Machine clock
frequency
F
MP
—
0.031 — 16.25 MHz When the main oscillation clock is used
0.25 — 4 MHz When the main CR clock is used
0.5 — 16 MHz When the main PLL clock is used
0.5 — 16 MHz When the main CR PLL clock is used
F
MPL
1.024 — 16.384 kHz When the sub-oscillation clock is used
3.125 — 50 kHz
When the sub-CR clock is used
F
CRL = 100 kHz