Cypress MB95710M Series - Page 146

MB95710M Series
MB95770M Series
Document Number: 002-09307 Rev. *D Page 145 of 172
FCH
(Main oscillation clock)
Divided by 2
Divided by 2
Divided by 2
FCRH
(Main CR clock)
FMCRPLL
(Main CR PLL clock)
FCL
(Suboscillation clock)
FCRL
(Sub-CR clock)
FMPLL
(Main PLL clock)
SCLK
(Source clock)
MCLK
(Machine clock)
Machine clock divide ratio select bits
(SYCC:DIV[1:0])
Clock mode select bits
(SYCC:SCS[2:0])
Division circuit
×
×
×
×
1
1/4
1/8
1/16
• Schematic diagram of the clock generation block
Operating voltage (V)
A/D converter operation range
5.5
3 MHz16 kHz 10 MHz 16.25 MHz
Source clock frequency (FSP/FSPL)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.8
1.5
0.0
≈
• Operating voltage - Operating frequency (TA = −40 °C to +85 °C)