Denon AVR-4520CI - Page 225

225
ADV7850
Pin No. Mnemonic Description
trilevel/bilevel input on the SCART or D-terminal connector.
AA23 VS_IN2/TRI6
T
he VS input signal is used for 5-wire timing mode. This ball can also be used as a
trilevel/bilevel input on the SCART or D-terminal connector.
AB1 GND Ground
AB2 TX_PVDD HDMI Tx digital supply (1.8V)
AB3
T
X_PLVDD HDMI Tx PLL digital supply (1.8V). It is important to ensure that this supply pin has a
clean voltage input.
AB4 SDVDD Memory interface supply
AB5 A11 SDRAM address line
AB6 A6 SDRAM address line
AB7 A2 SDRAM address line
AB8 CAS SDRAM interface Column Address Select Command Signal. One of four command
signals to the external SDRAM.
AB9 RAS SDRAM interface Row Address Select Command Signal. One of four command
signals to the external SDRAM.
AB10 VREF Termination reference voltage for memory interface
AB11 SDVDD Memory interface supply
AB12 LDQSN SDRAM lower data strobe compliment signal
AB13 DQ3 SDRAM data line
AB14 DQ10 SDRAM data line
AB15 DQ12 SDRAM data line
AB16 DQ14 SDRAM data line
AB17 GND Ground
AB18 SYNC1
T
his is a synchronization on green or luma input (SOG/SOY) used in embedded
synchronization mode.
AB19 AVIN3 Analog video mux input channel
AB20 GND Ground
AB21 SYNC2
T
his is a synchronization on green or luma input (SOG/SOY) used in embedded
synchronization mode.
AB22 AVIN6 Analog video mux input channel
AB23
T
RI4 Digital input capable of slicing bi-level or tri-level input from SCART or D-Connector.
AC1 GND Ground
AC2 TX_RTERM This signal sets the internal termination resistance. A 500R resistor between this ball
and GND should be used.
AC3
T
X_VDD33 HDMI Tx PLL Regulator Supply input (3.3V). This pin is an internal voltage regulator
input.
AC4 SDVDD Memory interface supply
AC5 A8 SDRAM address line
AC6 A4 SDRAM address line
AC7 A0 SDRAM address line
AC8 CS SDRAM interface Chip Select. SDRAM CS Enables and disables the command decoder
on the RAM. One of four command signals to the external SDRAM.
AC9 CKN SDRAM interface Dierential Clock Compliment Output. All address and control
output signals to the RAM should be sampled on the positive edge of CK and on the
negative edge of CKN.
AC10 C
K
SDRAM interface Dierential Clock Right Output. All address and control output
signals to the RAM should be sampled on the positive edge of CK and on the
negative edge of CKN.
AC11 SDVDD Memory interface supply
AC12 LDQS SDRAM lower data strobe true signal
AC13 DQ1 SDRAM data line
AC14 DQ9 SDRAM data line
AC15 DQ15 SDRAM data line
AC16 DQ13 SDRAM data line
AC17 GND Ground
AC18 AVIN1 Analog video mux input channel
AC19 AVIN2 Analog video mux input channel
AC20 GND Ground
AC21 AVIN4 Analog video mux input channel
AC22 AVIN5 Analog video mux input channel
AC23 GND Ground