ECS Motherboard

33
Using BIOS
Advanced Chipset Features
These items define critical timing parameters of the motherboard. You should leave the
items on this page at their default values unless you are very familiar with the technical
specifications of your system hardware. If you change the values incorrectly, you may
introduce fatal errors or recurring instability into your system.
Phoenix-AwardBIOS CMOS Setup Utility
Advanced Chipset Features
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DRAM Clock/Timing Control [Press Enter]
AGP & P2P Bridge Control [Press Enter]
Onchip AGP Control [Press Enter]
System BIOS Cacheable [Disabled]
Video RAM Cacheable [Disabled]
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Item Help
Menu Level
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: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help
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F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
DRAM Timing Control (By SPD)
Enables you to select the CAS latency time in HCLKs of 2, 2.5, or 3. The value is set at the
factory depending on the DRAM installed. Do not change the values in this field unless you
change specifications of the installed DRAM or the installed CPU.
• DRAM CAS Latency (2.5T): This item controls the timing delay (in clock
cycles) before the DRAM starts a read command after receiving it.
• RAS Active Time (tRAS) (6T): This item allows you to set the amount of time
a RAS can be kept open for multiple accesses. High figures will improve
performance.
DRAM Clock/Timing Control
Scroll to this item and press <Enter> to view the following screen:
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DRAM Timing Control [By SPD]
DRAM CAS Latency 2.5T
RAS Active Time (tRAS) 6T
RAS Precharge Time (tRP) 3T
RAS to CAS Delay (tRCD) 3T
Phoenix-AwardBIOS CMOS Setup Utility
DRAM Clock/Timing Control
Item Help
Menu Level
f
: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help
mnlk
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
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X
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