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Epson RX8111CE - 14.9. Flow Chart; 1) Power on initializing example

Epson RX8111CE
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RX8111CE
Page46
ETM61E-01
1) VLOW bit (Time Stamp VLOW)
This bit records the comparison result of V
BAT
vs V
LOW
at the moment of event.
Table 61 VLOW bit (Time Stamp VLOW)
VLOW
Data
Description
Read
0
V
BAT
> V
LOW
1
V
BAT
< V
LOW
2) VCMP bit (Time Stamp VCMP)
This bit records the comparison result of V
DD
vs V
BAT
(VCMP status) at the moment of event.
Table 62 VCMP bit (Time Stamp VCMP)
VCMP
Data
Description
Read
0
V
DD
> V
BAT
1
V
DD
< V
BAT
3) VDET bit (Time Stamp VDET)
This bit records the comparison result of V
DD
vs V
DET1
at the moment of event.
Table 63 VDET bit (Time Stamp VDET)
4) XST bit (Time Stamp X’tal Oscillation Stop)
This bit records either internal Crystal oscillation stop or not stop at the moment of event.
Table 64 XST bit (Time Stamp X’tal Oscillation Stop)
XST
Data
Description
Read
0
Normal Internal Crystal oscillation
1
Internal Crystal oscillation stops
14.8.6. RTC internal event triggered time stamp, multiple times stamp
In addition to EVIN pin input triggered , the RTC time stamp can be triggered by internal event.
Also, time stamp events are continuously recoded into RAM up to maximum 8 times.
To avoid unwanted timestamp event, ETS register should be reset to 0 before reading time stamp data (2hf ~ 29h, 40h ~ 47h).
(Refer to Figure36)
Table 65 Related register for internal event triggered time stamp, multiple times stamp
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
34h
Time Stamp Control 1
z
z
z
z
z
EISEL
TSCLR
TSRAM
35h
Time Stamp Control 2
z
z
z
ECMP
EDET
EVLOW
EXST
36h
Time Stamp Control 3
z
z
z
TSFUL
TSEMP
TSAD2
TSAD1
TSAD0

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