Espressif Systems ESP32-S3 - Page 11

Chapter 3. Schematic Checklist
Table IO Pad Status After Chip Initialization in the USB-OTG Download Boot Mode to determine whether R1
should be populated or not.
• The connection for 1.8 V, octal, o󰝗-package 󰝙ash/PSRAM is as shown in Figure ESP32-S3 Schematic for
O-Package 1.8 V Octal Flash/PSRAM.
• When only in-package 󰝙ash/PSRAM is used, there is no need to populate the resistor on the SPI traces or to
care the SPI traces.
Fig. 2: ESP32-S3 Schematic for O󰝗-Package 1.8 V Octal Flash/PSRAM
Any basic ESP32-S3 circuit design may be broken down into the following major building blocks:
• Power supply
• Chip power-up and reset timing
• Flash and PSRAM
• Clock source
• RF
• UART
• Strapping pins
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