Fluke 8021B - Page 41

8021
B
3-11. The
digital control
portion of
the
a
/
d
conversion
process is an
internal
function
of
U8,
and
is
keyed
to the
external
crystal frequency.
As a
result, the
conversion process is
continuously
repeated, and the
display is
updated at the
end
of
every
conversion cycle.
3-12.
A simplified
circuit
diagram of
the analog
portion of the a/d
converter is
shown in
Figure
3-2.
Each of
the switches
shown
represent analog
gates which are
operated
by the
digital
section of
the
a/d
converter. Basic
timing for
switch operation
and a
complete
measurement cycle are also
included in the
figure.
3-13.
Any
given
measurement
cycle
performed by the
a/d
converter can
be divided into
three
consecutive
time periods,
autozero
(AZ),
integrate (1NTEG),
and read.
Both
autozero and
integrate are
fixed
time periods
whose
lengths are
multiples of the clock
frequency. A
counter determines
the
length of both
time periods by
providing
an overflow
at the end
of every
10,000
clock pulses.
The read
period is a
variable time
which is
proportional
to the
unknown
input voltage.
The value
of the
voltage is determined by
counting the
number of
clock pulses
that occur
during the
read period.
3-14. During autozero a
ground
reference is
applied as an
input to the a/d
converter.
Under ideal
conditions the
output of
the
comparator
would
also go to
zero.
However,
input-offset-voitage
errors
accumulate
in the
amplifier loop, and
appear at the
comparator
output as an
error
voltage. This
error is
impressed across the AZ
capacitor
where it
is stored for
the remainder
of the
measurement cycle.
The stored
level is used to
provide
offset voltage
correction
during the
integrate and read
periods.
3-
1
5. The
integrate period
begins at
the end of
the
autozero period. As the
period begins,
the AZ
switch opens
and the
1NTEG switch
closes. This
applies
the unknown
input voltage
to the
input of the a/d
converter.
The voltage is
buffered
and passed on
to the integrator
to
determine the
charge rate
(slope) on
the 1NTEG
capacitor. By
the end of the
fixed
integrate
period the
capacitor is charged
to a level
proportional to the
unknown
input voltage. This
voltage is
translated to a
digital indication
by
discharging the
capacitor at a fixed
rate
during
the read
period, and
counting the
number of
clock pulses
that occur
before it
returns to
the original
autozero
level.
3-16. As the read
period
begins, the 1NTEG
switch opens and the
readswitch
closes. This
applies a known
reference
voltage to the
input of the
a/d converter. I
he polarity
of this
voltage is
automatically selected
to be
opposite that of
the unknown
input voltage, thus,
causing the
1NTEG
capacitor to
discharge at
a
fixed rate
(slope). When the
charge is
equal
to
the initial
starting point
(autozero
level), the
read period is
ended. Since
the discharge
slope
is fixed during
the read
period, the time
required
for discharge is
proportional to the
unknown
input voltage.
3-17.
The
autozero period
and, thus,
a
new measurement
cycle begins at
the end of the
read period. At
the same
time the
counter is
released for
operation by
transferring its
contents (previous
measurement
value)
to a series of
latches. This
stored data is
then
decoded
and
buffered
before being
used for
driving the
liquid crystal
display.
3-3