Fujitsu EVB JADE-­D - Page 13

Preliminary
13(45)
Prepared Document Number
Manfred Ortmann
Approved Checked Date Revision Storage
2009-10-05 PA 4.2 Mycable01
Pin Signal Function
35 MEM_XCS2 Chip Select 2
36 CPU_D10 Data
37 MEM_XCS0 Chip Select 0
38 CPU_D13 Data
39 CPU_A22 Address
40 CPU_A2 Address
41 CPU_A21 Address
42 CPU_A6 Address
43 MEM_XWR0 Write Strobe
44 CPU_A5 Address
45 CPU_A24 Address
46 CPU_A10 Address
47 MEM_RDY Ready input for slow device
48 CPU_A9 Address
49 APIXGND Ground for APIX signals
50 CPU_A14 Address
51 APIX_SDIN2 Serial Data Input 1 ( positive )
52 CPU_A13 Address
53 APIX_SDIN3 Serial Data Input 0 ( negative )
54 CPU_A18 Address
55 APIXGND Ground for APIX signals
56 CPU_A17 Address
57 APIX_SDOUT3 Serial Data Output 1 ( negative )
58 HOST_SPI_DI HOST SPI Data Input ( MOSI )
59 APIX_SDOUT2 Serial Data Output 1 ( positive )
60 HOST_SPI_DO HOST SPI Data Output ( MISO )
61 APIX_SDIN1 Serial Data Input 0 ( negative )
62 HOST_SPI_SS HOST SPI Slave Select
63 APIX_SDIN0 Serial Data Input 0 ( positive )
64 HOST_SPI_SCK HOST SPI Clock
65 APIXGND Ground for APIX signals
66 DCLKIN1 Video output interface 1 dot clock input
67 APIX_SDOUT1 Serial Data Output 0 ( negative )
68 SPI_DI0 SPI0 Master Data Input ( MISO )
69 APIX_SDOUT0 Serial Data Output 0 ( positive )
70 SPI_DO0 SPI0 Master Data Output ( MOSI )