Preliminary
14(45)
Prepared Document Number
Manfred Ortmann
Approved Checked Date Revision Storage
2009-10-05 PA 4.2 Mycable01
Pin Signal Function
71 APIXGND Ground for APIX signals
72 SPI_SS0 SPI0 Master Slave Select
73 VIN0_7 Video Capture Data Input 0 bit 7
74 SPI_SCK0 SPI0 Master serial clock
75 VIN0_4 Video Capture Data Input 0 bit 4
76 TSG_R_4 TCON Timing Signal
77 VIN0_3 Video Capture Data Input 0 bit 3
78 TSG_R_5 TCON Timing Signal
79 VIN0_5 Video Capture Data Input 0 bit 5
80 TSG_R_6 TCON Timing Signal
81 VIN0_6 Video Capture Data Input 0 bit 6
82 DCLKP RSDS Clock Output CLKp, in TTL Mode
83 VIN0_1 Video Capture Data Input 0 bit 1
84 DCLKN RSDS Clock Output CLKn, in TTL Mode
85 VIN0_2 Video Capture Data Input 0 bit 2
86 DE0 TCON Bypass: DE/CSYNC of DISPL0, TCON:TSG_2
87 VIN0_8 Video Capture 0 Clock
88 HSYNC0 Video Capture 0 Horizontal Syncronisation
89 VIN0_0 Video Capture Data Input 0 bit 0
90 GVO0 Video output interface 0 graphics / video switch
91 TSG_R_7 TCON Timing Signal
92
VSYNC0 TCON Bypass: Video output interface 0 vertical sync
output vertical sync input in external sync mode
93 ATST_R APIX analog Test Clock
94 DOUTB1_R_5 Digital RGB output1 with serial resistor
95 PWMO2 PWM Output
96 DOUTB1_R_2 Digital RGB output1 with serial resistor
97 DOUTB1_R_3 Digital RGB output1 with serial resistor
98 DOUTG1_R_3 Digital RGB output1 with serial resistor
99 DOUTB1_R_4 Digital RGB output1 with serial resistor
100 DOUTB1_R_6 Digital RGB output1 with serial resistor
101 DOUTB1_R_7 Digital RGB output1 with serial resistor
102 DOUTG1_R_7 Digital RGB output1 with serial resistor
103 DOUTG1_R_2 Digital RGB output1 with serial resistor
104 DOUTG1_R_4 Digital RGB output1 with serial resistor
105 DOUTG1_R_5 Digital RGB output1 with serial resistor
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