Fujitsu EVB JADE-­D - Page 17

Preliminary
17(45)
Prepared Document Number
Manfred Ortmann
Approved Checked Date Revision Storage
2009-10-05 PA 4.2 Mycable01
Pin Signal Function
34 ADCGND Ground for ADC signals
35 AD_VRL0 Reference voltage "L" input
36 AD_VRH1 Reference voltage "H" input 1
37 AD_VR0 Reference output
38 AD_VIN1 A/D analog input, channel 1
39 AD_VIN0 A/D analog input, channel 0
40 AD_VRH0 Reference voltage "H" input 0
41 GND Ground
42
OPT_PIN_0 A/D analog input, channel 2 or
TESTMODE 2
43
DISP_P_R_10 RSDS Output 10p, in TTL Mode
Default=DOUTB0_4
44
OPT_PIN_1 A/D analog input, channel 3 or
VINITHI
45
DISP_N_R_10 RSDS Output 10n, in TTL Mode
Default=DOUTB0_5
46 VCC12 1.2 V from CPU core voltage regulator
47
DISP_P_R_7 RSDS Output 7p, in TTL Mode
Default=DOUTG0_6
48 VCC12 1.2 V from CPU core voltage regulator
49
DISP_N_R_7 RSDS Output 7n, in TTL Mode
Default=DOUTG0_7
50
DISP_P_R_0 RSDS Output 0p, in TTL Mode
Default=DOUTR0_0
51
DISP_P_R_8 RSDS Output 8p, in TTL Mode
Default=DOUTB0_0
52
DISP_N_R_0 RSDS Output 0n, in TTL Mode
Default=DOUTR0_1
53
DISP_N_R_8 RSDS Output 8n, in TTL Mode
Default=DOUTB0_1
54
DISP_P_R_1 RSDS Output 1p, in TTL Mode
Default=DOUTR0_2
55
DISP_P_R_9 RSDS Output 9p, in TTL Mode
Default=DOUTB0_2
56
DISP_N_R_1 RSDS Output 1n, in TTL Mode
Default=DOUTR0_3
57
DISP_N_R_9 RSDS Output 9n, in TTL Mode
Default=DOUTB0_3
58
DISP_P_R_2 RSDS Output 2p, in TTL Mode
Default=DOUTR0_4