GE N60 - Page 233

GE Multilin N60 Network Stability and Synchrophasor Measurement System 5-115
5 SETTINGS 5.4 SYSTEM SETUP
5
The figure shows an example of an N60 using four Logical Device PMUs (Logical Device 2 through 5) and four aggrega-
tors. The control blocks for the aggregators are located in LD1. A 64 char LDName setting is provided.
Figure 5–32: N60 EXAMPLE FOR FOUR LOGICAL DEVICE PMUS
Precise time input to the relay from the international time standard, via either IRIG-B or PTP, is vital for correct syn-
chrophasor measurement and reporting. For IRIG-B, a DC level shift IRIG-B receiver must be used for the phasor
measurement unit to output proper synchrophasor values.
Depending on the applied filter, the Synchrophasors that are produced by PMUs are classified as either P (protection) or M
(Measurement) class Synchrophasors. Synchrophasors available within the UR that have no filtering applied are classified
as NONE, which within the standard is classified as PRES OR UNKNOWN under the Calculation Method - ClcMth. Each
Logical Device PMU supports one MxxMMXU, MxxMSQI, PxxxMMXU , PxxxMSQI, NxxMMXU, and one NxxMSQI logical
node.
Figure 5–33: LOGICAL NODES SUPPORTED IN EACH LOGICAL DEVICE
The following is a summary of LNs that are in each Logical Device (LD2 through LD7):
- PxxxMMXU1 ClcMth = P-Class (Note Vaux is mapped to Vneut of MMXU)
- PxxxMSQI1 ClcMth = P-CLASS
- MxxMMXU1 ClcMth = M-Class (Note Vaux is mapped to Vneut of MMXU)
- MxxMSQI1 ClcMth = M-CLASS
- NxxMMXU1 ClcMth = M-Class (Note Vaux is mapped to Vneut of MMXU)
NOTE