HackRF
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# CLK1_PDN=0 (powered up)
# MS1_INT=1 (integer mode)
# MS1_SRC=0 (PLLA as source for MultiSynth 1)
# CLK1_INV=0 (not inverted)
# CLK1_SRC=3 (MS1 as input source)
# CLK1_IDRV=3 (8mA)
[0xC0 16 0x4F 0x4F 0x80 0x80 0x80 0x80 0x80 0x80]
# Enable CLK0 output only.
[0xC0 3 0xFC]
24.1.5 Si5351 output phase relationships
Tested CLK4 and CLK5 (integer division only):
With CLK4 set to MS4 and CLK5 set to MS5, even with both multisynths configured identically, there was no consistent
phase between the two. Once started, the clocks maintained relative phase with each other, but when stopped and
restarted the initial phase offset was unpredictable.
With CLK4 and CLK5 both set to MS4, the phase of both outputs was identical when no output (R) divider was
selected. When an output divider was selected on both MS4 and MS5, the relative phase became predictable only
within the constraints of the divider (e.g. with R=2 the relative phase was always either 0 or half a cycle, with R=4 the
relative phase was always either 0, a quarter, a half, or three quarters of a cycle). With R=1 on MS4 and R=2 on MS5,
the two outputs were consistently in phase with each other. The output (R) dividers supposedly tied to the multisynths
are actually tied to the outputs.
24.1. Si5351 I2C 93
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