A-ISiCL CM-5RTD Delay Configuration ACS-160 Series & STL-160 Series T1 Multiplexer
Version 2.1, April 2011
Harris Corporation A-5
Intraplex Products
:C2:SET:P2=100000000; Select smooth change
:C2:SET:P4=B10011110; Set low-order 8 bits for 29.95 milliseconds (no change in high-order 8
bits is required)
A.5 Delay Setting with RS-422 Control Port
This method uses the RS-422 control “port” to change the delay value. The control port is part of the
physical external timing input connector. Table 2-10 shows the MA-215/MA-217B/MA-235-1/MA-235-2
timing in port pin assignments.
The control port is a receive-only RS-422/RS-485 serial port configured to accept an asynchronous
9600 bps data stream with these elements:
● One start bit
● Eight data bits
● No parity
● One stop bit
The control port recognizes four different information bytes. Each of these four bytes consists of two
identifying bits and six data bits (Figure A-2); the 24 data bits contained in these four bytes are
identical to the 24 bits in P02, P03, and P04 under ISiCL (Section A.1 – Delay P Codes). The least
significant (right-hand) bit is transmitted first. As when using P codes, it is best to send the most
significant bits first.
Figure A-2. RS-422 Control Port Information Bytes
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