4 – Setup & Configuration ACS-160 Series & STL-160 Series T1 Multiplexer Installation & Operation
Version 2.11, August 2011
Harris Corporation 4-13
Intraplex Products
4.4.3 Timing Status Functions
Several functions in the BLNK and RVU1 groups provide additional information on timing status.
To inspect these timing status functions, perform these steps:
1. Press down repeatedly on the GROUP switch until the desired group (BLNK or RVU1) appears on
the display.
2. Press down repeatedly on the SET/NEXT switch to view the contents of the selected group. Table
3-6 lists the meanings of these functions.
Table 4-6. Timing Status Functions
Function Group Description
Ftim BLNK Fallback timing – Ftim in the BLNK group indicates that transmitter is in its fallback timing
mode.
TXLk RVU1 Transmit lock – The bi-level ON/OFF indicator light signifies status of T1 transmitter PLL.*
Transmitter PLL is locked
Transmitter PLL is not locked
TxRx RVU1 Transmit/Receive lock. When the transmit/receive lock function is displayed, the bi-level
ON/OFF indicator lights signifies whether the transmitter timing is synchronized to
incoming T1 signal timing.
Transmitter and receiver timing clocks are locked.
Transmitter and receiver timing clocks are not locked.
If top and bottom indicator lights are blinking on and off, transmit and receive
signals are not locked but their frequencies are close. In this case, each flash
of red (bottom) light corresponds to relative phase change of one T1 Unit
Interval (UI), which is 648ns. Relative phase change of one UI is called a “bit
slip” by some T1 test set manufacturers.
* When a CM-5RB module uses internal (INT) timing, whether primary or fallback, the TxLk function is
normally off. However, when any other timing mode is in use (EXT, THRU, LOOP), the TxLK function is
normally on and a fault condition is indicated when it is off.
4.4.4 Timing Mode Use
Figures 4-4 through 4-8 show appropriate uses of each of the four T1 transmitter timing modes. In
ACS-160 Series systems synchronized to the digital network, both terminal multiplexers are normally
be loop timed (Figure 4-4 and Figure 4-6). In systems timed from one end and not synchronized to
the carrier's network, one terminal is internally (or externally) timed while the other is loop timed
(Figures 4-5, 4-7, and 4-8). Figure 4-8 shows an ACS-160 Series system with an external timing
source.