Heathkit SW-7800 - Page 35

Heathkit
Page
123
U201
pins
4
through
6,
8,
and
9
select
the
digit
while
pins
15
through
17
and
19
through
22
select
the
segment
to
be
displayed.
Pin
23
drives
the
deci-
mal
point,
Input
to
the
frequency counter
is
applied
to
pin
28
and
a
logic
low
measurement-in-progress
signal
is
available
at
pin
2.
Programmable
features
of
U201
include
decimal
point
location,
which
is
set
by
R201.
R202
programs
a
constant
decimal
point
display
at
digit
4
(digit
0
is
for
100
Hz
resolution,
which
is
not
used
in
this
Receiver).
R203
programs
the
internal
time-base
counter
fora
100
millisecond
sample
gate
time
The
display
circuit
board
is
driven
directly
by
U201
Each
digit
is
multiplexed
at
a
500
Hz
rate
through
internal
circuitry.
Built-in
blanking
between
digits
is
also
provided
to
eliminate
any
ghosting
of
the
dis.
play.
U201
turns
on
each
digit
of
the
display
and
selects
the
proper
segments.
The
displays
are
common-cathode
LEDs,
and each
display
segment
is
connected
in
parallel
with
the
same
segment
on
all
other
displays.
U201
supplies
a
0-volt
pulse
to
the
cathode
lead
to
turn
each
digit
on,
after
it
applies
5
volts
to
the
anode
segments
to
select the
appropriate
segments.
Display
Circuit
‘he
10
MHz
time-base
signal
coming
from
U201
is
coupled
through
buffer
transistor
Q203
to
quintupler
Qz12,
and
to
amplifier
Q204
for
the
phase
detector.
Components
C228,
L202,
C224,
L203, C231,
and
C232
select
the
fifth
harmonic
of
the
time-base
sig-
nal.
This
50
MHz
signal
is
buffered
by
Q213
and
Qa14
and
is
then
applied
to
mixer
Q221
for
the
VCO
loop.
The
signal
coming
from
Q214
is
also
applied
to
Q215,
where
it
is
mixed
with
the
VCO
signal
com-
ing
from
Q222,
The
605
Hz
to
30.455
MHz
difference
frequency
is
coupled
through
a
low-pass
filter,
consisting
of
L204, L205,
L206, C244,
C245,
and
C246,
to
four
amplifiers.
Q216
through
Q219
boost
the
signal
to
TTL
levels
for
divider
U213.
U213
divides
the
signal
by
10
before
it
is
applied
to
pin
12
of
U202A,
the
input
gate
for
U201.
The
signal
at
this
point
is
455
kHz
above
the
actual
received
frequency.
With the
counter
sample
gate
at
100 milliseconds
(.1
second)
and
the
division
by
10
of
U213,
this
means
4550
(instead
of
455,000)
must
be
subtracted
from
the
sig.
nal
before
you
can
obtain
the
correct
readout.
The
output
from
U213
is
also
coupled
to
an
up-counter,
formed
by
U208, U209, U211,
and
U212, where
this
correction
is
made.
Normally,
U202
pin
11
is
low
and
allows
the
output
of
U213
to
reach
the
counter
input
of
U201.
When
a
count
period
begins,
U201
pin
2
goes
low
to
indi
cate
that
a
measurement
is
in
progress.
U202C
in
verts
this
low, which
is
differentiated
by
C207 and
R208.
The
resulting
pulse
is
applied
to U202
pin
6,
where
it
sets
RS
flip-flop
U202D.
This
disables
U202A
and
prevents
any
further
signal
from
reach
ing
the
input
of U201
The
positive
pulse
coming
from
U202C
also
causes
a
binary
up-counter,
formed
by
U208,
U209,
U211,
and
U212,
to
load
a
preset
value
of
EE38
hex
(60984
decimal)
and
begin
to
count.
After
4551
counts,
the
up-counter
reaches
terminal
value
and
resets
to
0000
hex.
At
this
point,
a
positive
(carry)
pulse
is
sent
from
U212
pin
15
to
U202
pin
2.
This
resets
the
RS
flip-flop
and
allows
the
output
of
U213
to
pass
through
U202A
to
the
counter.
This
effectively
sub-
tracts 455,
since
it
prevents
U201
from
seeing
the
first
455
Hz.
U201
then
counts
and
displays
the
cor-
rect
received
frequency.
A
special
troubleshooting
feature
of
the
circuit
al-
lows
it
to
be
used
as
a
straight
frequency
counter
By
connecting
jumper
wire
AA
to
point
K,
U202
pin
11
is
grounded.
This
keeps
the
input
gate
enabled
and
allows
U201
to
receive
any
input
from
the
loop.
The
frequency
of
a
signal
connected
to
point
E,
at
Q219,
will
be
displayed
on
the
front
panel
display.
The
signal
must
pass
through
U213,
due
to
the
.1
second
sample
gate
period
of
U201,
or
the
indication
will
be
high
by
a
factor
of
10.
The
display
circuit,
when
it
is
used
as
a
frequency
counter,
will indicate
frequencies
up
to 40
MHz with
less
than
30
millivolts
input
at
point
E
VCO
Phase-Locked
Loop
.
Capacitor
C237
couples
the
50
MHz
reference
signal
coming
from
the
display
circuit
to
point
R
for
use
as
LO
#2
by
the
second
mixer.
C258
also
couples
the
signal
to
mixer
transistor
Q221.
In
addition,
257
couples
the
VFO
signal
coming
from the
con-
troller
circuit
board
to
mixer
transistor
Q221.
This
results
in
a
difference
frequency
between
43.455
and
44.455
MHz,
which
passes
through
a
bandpass
filter
formed
by
C262,
1207,
C263,
C264,
C265,
and
L208