8.4 Communication Methods
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Status Byte Register (STB)
During serial polling, the contents of the 8-bit Status Byte Register are sent from
the instrument to the controller.
When any Status Byte Register bit enabled by the Service Request Enable Reg-
ister has switched from 0 to 1, the MSS bit becomes 1. Consequently, the SRQ
bit is set to 1, and a service request is dispatched.
The SRQ bit is always synchronous with service requests, and is read and simul-
taneously cleared during serial polling. Although the MSS bit is only read by an
*STB? query, it is not cleared until a clear event is initiated by the *CLS com-
mand.
Service Request Enable Register (SRER)
This register masks the Status Byte Register. Setting a bit of this register to 1
enables the corresponding bit of the Status Byte Register to be used.
Bit 7 unused
Bit 6
SRQ
MSS
Set to 1 when a service request is dispatched.
This is the logical sum of the other bits of the Status Byte Regis-
ter.
Bit 5
ESB
Standard Event Status (logical OR) bit
This is logical sum of the Standard Event Status Register.
Bit 4
MAV
Message available
Indicates that a message is present in the output queue.
Bit 3 unused
Bit 2 unused
Bit 1
ESB1
Event Status (logical OR) bit 1
This is the logical sum of Event Status Register 1.
Bit 0
ESB0
Event Status (logical OR) bit 0
This is the logical sum of Event Status Register 0.
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