The START bit in the ADCR register is used to start and reset the A/D converter. When the
microcontroller sets this bit from low to high and then low again, an analog to digital conversion cy
-
cle will be initiated. When the START bit is brought from low to high but not low again, the EOCB bit
in the ADCR register will be set to a ²1² and the analog to digital converter will be reset. It is the
START bit that is used to control the overall on/off operation of the internal analog to digital con
-
verter.
The EOCB bit in the ADCR register is used to indicate when the analog to digital conversion pro
-
cess is complete. This bit will be automatically set to ²0² by the microcontroller after a conversion
cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the inter
-
48
A/D Type MCU
A D C R R e g i s t e r ( e x c l u d i n g H T 4 6 R 4 7 / H T 4 6 C 4 7 )
S e l e c t A / D c h a n n e l
b 7 b 0
S T A R T
P C R 2
P C R 1 P C R 0
A C S 2 A C S 1
A C S 0
A C S 2
0
0
0
0
1
1
1
1
A C S 1
0
0
1
1
0
0
1
1
A C S 0
0
1
0
1
0
1
0
1
: A N 0
: A N 1
: A N 2
: A N 3
: A N 4
: A N 5
: A N 6
: A N 7
P o r t B A / D c h a n n e l c o n f i g u r a t i o n s
P C R 2
0
0
0
0
1
1
1
1
P C R 1
0
0
1
1
0
0
1
1
P C R 0
0
1
0
1
0
1
0
1
: P o r t B A / D c h a n n e l s - a l l o f f
: P B 0 e n a b l e d a s A N 0
: P B 0 ~ P B 1 e n a b l e d a s A N 0 ~ A N 1
: P B 0 ~ P B 2 e n a b l e d a s A N 0 ~ A N 2
: P B 0 ~ P B 3 e n a b l e d a s A N 0 ~ A N 3
: P B 0 ~ P B 4 e n a b l e d a s A N 0 ~ A N 4
: P B 0 ~ P B 5 e n a b l e d a s A N 0 ~ A N 5
: P B 0 ~ P B 7 e n a b l e d a s A N 0 ~ A N 7
E n d o f A / D c o n v e r s i o n f l a g
1 : n o t e n d o f A / D c o n v e r s i o n - A / D c o n v e r s i o n w a i t i n g o r i n p r o g r e s s
0 : e n d o f A / D c o n v e r s i o n - A / D c o n v e r s i o n e n d e d
S t a r t t h e A / D c o n v e r s i o n
0
®
1
®
0 : S t a r t
0
®
1 : R e s e t A / D c o n v e r t e r a n d s e t E O C B t o " 1 "
E O C B
A D C R R e g i s t e r ( H T 4 6 R 4 7 / H T 4 6 C 4 7 )
S e l e c t A / D c h a n n e l
b 7 b 0
S T A R T
P C R 2
P C R 1 P C R 0
A C S 2 A C S 1 A C S 0
A C S 2
0
0
0
0
1
A C S 1
0
0
1
1
X
A C S 0
0
1
0
1
X
: A N 0
: A N 1
: A N 2
: A N 3
: u n d e f i n e d , c a n n o t b e u s e d
P o r t B A / D c h a n n e l c o n f i g u r a t i o n s
P C R 2
0
0
0
0
1
P C R 1
0
0
1
1
X
P C R 0
0
1
0
1
X
: P o r t B A / D c h a n n e l s - a l l o f f
: P B 0 e n a b l e d a s A N 0
: P B 0 ~ P B 1 e n a b l e d a s A N 0 ~ A N 1
: P B 0 ~ P B 2 e n a b l e d a s A N 0 ~ A N 2
: P B 0 ~ P B 3 e n a b l e d a s A N 0 ~ A N 3
E n d o f A / D c o n v e r s i o n f l a g
1 : n o t e n d o f A / D c o n v e r s i o n - A / D c o n v e r s i o n w a i t i n g o r i n p r o g r e s s
0 : e n d o f A / D c o n v e r s i o n - A / D c o n v e r s i o n e n d e d
S t a r t t h e A / D c o n v e r s i o n
0
®
1
®
0 : S t a r t
0
®
1 : R e s e t A / D c o n v e r t e r a n d s e t E O C B t o " 1 "
E O C B
To Next Page
Loading...