When the system enters the HALT mode the system oscillator will be stopped to reduce power con
-
sumption. However, it is important to remember that if the internal WDT oscillator is enabled this
will keep running and result in a small amount of power being consumed. In addition if the A/D con
-
verter is used, even though the system oscillator has been stopped there will still be some power
consumption associated with the A/D circuitry. Therefore to minimize power consumption when in
the HALT mode, the A/D converter should be first disabled by clearing all the PCR bits in the
ADCR register.
The system can leave the HALT mode by means of a reset, an external interrupt, an external fall
-
ing edge signal on Port A or a WDT overflow. A reset will initialize a chip reset and a WDT overflow
will initialize a WDT time-out Reset from HALT but by examining the TO and PDF flags the source
of the reset can be determined. The PDF flag is cleared by a system power-up or executing the
²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only resets the Program Counter and SP; the
other flags remain in their original status.
Port A wake-up and external interrupt wake-up methods can be considered as a continuation of
normal execution. Each bit in Port A can be independently selected to wake-up the device by con
-
figuration option. Awakening from an I/O port stimulus, the program will resume execution at the
next instruction. If the system is woken up via an external interrupt, two possibilities may occur. If
the external interrupt is disabled or the external interrupt is enabled but the stack is full, the pro
-
gram will resume execution at the next instruction. If the external interrupt is enabled and the stack
is not full, the regular interrupt response takes place. If the external interrupt request flag is set to
²1² before entering the HALT mode, the wake-up function of the related interrupt will be disabled.
Once a wake-up event occurs, it takes 1024 system clock periods to resume normal operation. In
other words, a dummy period will be inserted after a wake-up. If the wake-up results from an exter
-
nal interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one
or more cycles. If the wake-up results in the next instruction execution, this will be executed imme-
diately after the dummy period is finished.
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise. It oper-
ates by providing a ²chip reset² when the WDT counter overflows. The WDT clock is supplied by
one of two sources selected by configuration option: its own self contained dedicated internal
WDT oscillator or the instruction clock which is the system clock divided by 4. Note that if the WDT
configuration option has been disabled, then any instruction relating to its operation will result in
no operation.
In the A/D series of microcontrollers, all watchdog timer options, such as enable/disable, WDT
clock source, and if applicable clock source division ratios are all selected through configuration
options. There are no internal registers associated with the WDT in the A/D series. One of the
WDT clock sources is an internal oscillator which has an approximate period of 65ms at a supply
voltage of 5V. However, it should be noted that this specified internal clock period can vary with
VDD, temperature and process variations. The other WDT clock source option is the instruction
clock which is the system clock divided by four (f
SYS
/4). Whether the WDT clock source comes
from its own internal WDT oscillator, or from the instruction clock, it is further divided by an internal
74
A/D Type MCU
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