Holtek HT66F30 - Page 114

Rev. 2.50 114 June 22, 2017 Rev. 2.50 115 June 22, 2017
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
TMnC0 Register
Bit 7 6 5 4 3 2 1 0
Name TnPAU TnCK2
TnCK1 TnCK0 TnON TnRP2 TnRP1 TnRP0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit7 TnPAU:TMnCounterPauseControl
0:Run
1:Pause
Thecountercanbepausedbysettingthisbithigh.Clearingthebittozerorestores
normalcounteroperation.WheninaPauseconditiontheTMwillremainpoweredup
andcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbit
changesfromlowtohighandresumecountingfromthisvaluewhenthebitchanges
toalowvalueagain.
Bit6~4 TnCK2~TnCK0:SelectTMnCounterclock
000:f
SYS
/4
001:f
SYS
010:f
H
/16
011:f
H
/64
100:f
TBC
101:Undened
110:TCKnrisingedgeclock
111:TCKnfallingedgeclock
ThesethreebitsareusedtoselecttheclocksourcefortheTM.SelectingtheReserved
clockinputwilleffectivelydisabletheinternalcounter.Theexternalpinclocksource
canbechosentobeactiveontherisingorfallingedge.Theclocksourcef
SYS
isthe
systemclock,whilef
H
andf
TBC
areotherinternalclocks,thedetailsofwhichcanbe
foundintheoscillatorsection.
Bit3 TnON:TMnCounterOn/OffControl
0:Off
1:On
Thisbitcontrolstheoverallon/offfunctionoftheTM.Settingthebithighenablesthe
countertorun,clearingthebitdisablestheTM.Clearingthisbittozerowillstopthe
counterfromcountingandturnofftheTMwhichwillreduceitspowerconsumption.
Whenthebitchangesstatefromlowtohightheinternalcountervaluewillberesetto
zero,howeverwhenthebitchangesfromhightolow,theinternalcounterwillretain
itsresidualvalue.
IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillbereset
toitsinitialcondition,asspeciedbytheTnOCbit,whentheTnONbitchangesfrom
lowtohigh.
Bit2~0 TnRP2~TnRP0:TMnCCRP3-bitregister,comparedwiththeTMnCounterbit9~bit7
ComparatorPMatchPeriod
000:1024TMnclocks
001:128TMnclocks
010:256TMnclocks
011:384TMnclocks
100:512TMnclocks
101:640TMnclocks
110:768TMnclocks
111:896TMnclocks
ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,which
arethencomparedwiththeinternalcounter'shighestthreebits.Theresultofthis
comparisoncanbeselectedtocleartheinternalcounteriftheTnCCLRbitissetto
zero.SettingtheTnCCLRbittozeroensuresthatacomparematchwiththeCCRP
valueswillresettheinternalcounter.AstheCCRPbitsareonlycomparedwiththe
highestthreecounterbits,thecomparevaluesexistin128clockcyclemultiples.
Clearingallthreebitstozeroisineffectallowingthecountertooverflowatits
maximumvalue.