Holtek HT66F30 - Port a Wake-�P; I;O Port Control Registers

Rev. 2.50 88 June 22, 2017 Rev. 2.50 89 June 22, 2017
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
PGPU Register
• HT66F60
Bit 7 6 5 4 3 2 1 0
Name — — — — — —
D1 D0
R/W — — — — — — R/W R/W
POR — — — — — — 0 0
Bit7~2 Unimplemented,readas“0”
Bit1~0 PGPU:PortGbit1~bit0Pull-HighControl
0:Disable
1:Enable
Port A Wake-up
TheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreserves
power,afeaturethatisimportantforbatteryandotherlow-powerapplications.Variousmethods
existtowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePort
Apinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenup
viaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeature
usingthePAWUregister.
PAWU Register
Bit 7 6 5 4 3 2 1 0
Name
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit7~0 PAWU :PortAbit7~bit0Wake-upControl
0:Disable
1:Enable
I/O Port Control Registers
EachI/OporthasitsowncontrolregisterknownasPAC~PGC,tocontroltheinput/output
configuration.Withthiscontrolregister,eachCMOSoutputorinputcanbereconfigured
dynamicallyundersoftwarecontrol.EachpinoftheI/Oportsisdirectlymappedtoabitinits
associatedportcontrolregister.FortheI/Opintofunctionasaninput,thecorrespondingbitofthe
controlregistermustbewrittenasa"1".Thiswillthenallowthelogicstateoftheinputpintobe
directlyreadbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa"0",
theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructions
canstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfact
onlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.
PAC Register
Bit 7 6 5 4 3 2 1 0
Name
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR
1 1 1 1 1 1 1 1