Rev. 2.50 26 June 22, 2017 Rev. 2.50 27 June 22, 2017
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
System Architecture
Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributed
totheirinternalsystemarchitecture.Therangeofdevicestakeadvantageoftheusualfeaturesfound
withinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.
Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstruction
executionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withthe
exceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyallinstructionset
operations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,
branchdecisions,etc.TheinternaldatapathissimpliedbymovingdatathroughtheAccumulator
andtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectly
orindirectlyaddressed.Thesimpleaddressingmethodsoftheseregistersalongwithadditional
architecturalfeaturesensurethataminimumofexternalcomponentsisrequiredtoprovidea
functionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakesthe
devicesuitableforlow-cost,high-volumeproductionforcontrollerapplications.
Clocking and Pipelining
Themainsystemclock,derivedfromeitheraHXT,LXT,HIRC,LIRCorERCoscillatoris
subdividedintofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounteris
incrementedatthebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.The
remainingT2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4
clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakes
placeinconsecutiveinstructioncycles,thepipeliningstructureofthemicrocontrollerensuresthat
instructionsareeffectivelyexecutedinoneinstructioncycle.Theexceptiontothisareinstructions
wherethecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhich
casetheinstructionwilltakeonemoreinstructioncycletoexecute.
System Clocking and Pipelining