Holtek HT66F30 - Watchdog Timer Operation

Rev. 2.50 68 June 22, 2017 Rev. 2.50 69 June 22, 2017
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
Watchdog Timer Operation
TheWatchdogTimeroperatesbyprovidingadeviceresetwhenitstimeroverows.Thismeans
thatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallyclearthe
WatchdogTimerbeforeitoverowstopreventtheWatchdogTimerfromexecutingareset.Thisis
doneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumps
toanunkownlocation,orentersanendlessloop,theseclearinstructionswillnotbeexecutedinthe
correctmanner,inwhichcasetheWatchdogTimerwilloverowandresetthedevice.Someofthe
WatchdogTimeroptions,suchasenable/disable,clocksourceselectionandclearinstructiontype
areselectedusingcongurationoptions.Inadditiontoacongurationoptiontoenable/disablethe
WatchdogTimer,therearealsofourbits,WDTEN3~WDTEN0,intheWDTCregistertoofferan
additionalenable/disablecontroloftheWatchdogTimer.TodisabletheWatchdogTimer,aswell
asthecongurationoptionbeingsettodisable,theWDTEN3~WDTEN0bitsmustalsobesetto
aspecicvalueof"1010".AnyothervaluesforthesebitswillkeeptheWatchdogTimerenabled,
irrespectiveofthecongurationenable/disablesetting.Afterpoweronthesebitswillhavethevalue
of1010.IftheWatchdogTimerisuseditisrecommendedthattheyaresettoavalueof0101for
maximumnoiseimmunity.NotethatiftheWatchdogTimerhasbeendisabled,thenanyinstruction
relatingtoitsoperationwillresultinnooperation.
WDT Conguration Option WDTEN3~WDTEN0 Bits WDT
WDT Enable ×××× Enable
WDT Disable
Except 1010 Enable
WDT Disable
1010 Disable
Watchdog Timer Enable/Disable Control
Undernormalprogramoperation,aWatchdogTimertime-outwillinitialiseadeviceresetandset
thestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimer
time-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStack
Pointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.
Therstisanexternalhardwarereset,whichmeansalowlevelontheRESpin,thesecondisusing
theWatchdogTimersoftwareclearinstructionsandthethirdisviaaHALTinstruction.
TherearetwomethodsofusingsoftwareinstructionstocleartheWatchdogTimer,oneofwhichmust
bechosenbycongurationoption.Therstoptionistousethesingle"CLRWDT"instructionwhile
thesecondistousethetwocommands"CLRWDT1"and"CLRWDT2".Fortherstoption,a
simpleexecutionof"CLRWDT"willcleartheWDTwhileforthesecondoption,both"CLRWDT1"
and"CLRWDT2"mustbothbeexecutedalternatelytosuccessfullycleartheWatchdogTimer.
Notethatforthissecondoption,if"CLRWDT1"isusedtocleartheWatchdogTimer,successive
executionsofthisinstructionwillhavenoeffect,onlytheexecutionofa"CLRWDT2"instruction
willcleartheWatchdogTimer.Similarlyafterthe"CLRWDT2"instructionhasbeenexecuted,only
asuccessive"CLRWDT1"instructioncancleartheWatchdogTimer.
Themaximumtimeoutperiodiswhenthe2
15
divisionratioisselected.Asanexample,witha
32.768kHzLXToscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround
1secondforthe2
15
divisionratio,andaminimumtimeoutof7.8msforthe2
8
divisionration.Ifthe
f
SYS
/4clockisusedastheWatchdogTimerclocksource,itshouldbenotedthatwhenthesystem
enterstheSLEEPorIDLE0Mode,thentheinstructionclockisstoppedandtheWatchdogTimer
mayloseitsprotectingpurposes.Forsystemsthatoperateinnoisyenvironments,usingthef
SUB

clocksourceisstronglyrecommended.