Rev. 2.50 124 June 22, 2017 Rev. 2.50 125 June 22, 2017
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
10-bit Standard TM Register List – HT66F20
• TM1C0 Register – 10-bit STM
Bit 7 6 5 4 3 2 1 0
Name
T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit7 T1PAU:TM1CounterPauseControl
0:Run
1:Pause
Thecountercanbepausedbysettingthisbithigh.Clearingthebittozerorestores
normalcounteroperation.WheninaPauseconditiontheTMwillremainpoweredup
andcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbit
changesfromlowtohighandresumecountingfromthisvaluewhenthebitchanges
toalowvalueagain.
Bit6~4 T1CK2~T1CK0:SelectTM1Counterclock
000:f
SYS
/4
001:f
SYS
010:f
H
/16
011:f
H
/64
100:f
TBC
101:Undened
110:TCK1risingedgeclock
111:TCK1fallingedgeclock
ThesethreebitsareusedtoselecttheclocksourcefortheTM.SelectingtheReserved
clockinputwilleffectivelydisabletheinternalcounter.Theexternalpinclocksource
canbechosentobeactiveontherisingorfallingedge.Theclocksourcef
SYS
isthe
systemclock,whilef
H
andf
TBC
areotherinternalclocks,thedetailsofwhichcanbe
foundintheoscillatorsection.
Bit3 T1ON:TM1CounterOn/OffControl
0:Off
1:On
Thisbitcontrolstheoverallon/offfunctionoftheTM.Settingthebithighenablesthe
countertorun,clearingthebitdisablestheTM.Clearingthisbittozerowillstopthe
counterfromcountingandturnofftheTMwhichwillreduceitspowerconsumption.
Whenthebitchangesstatefromlowtohightheinternalcountervaluewillberesetto
zero,howeverwhenthebitchangesfromhightolow,theinternalcounterwillretain
itsresidualvalueuntilthebitreturnshighagain.
IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillbereset
toitsinitialcondition,asspeciedbytheT1OCbit,whentheT1ONbitchangesfrom
lowtohigh.
Bit2~0
T1RP2~T1RP0:TM1CCRP3-bitregister,comparedwiththeTM1Counterbit9~bit7
ComparatorPMatchPeriod
000:1024TM1clocks
001:128TM1clocks
010:256TM1clocks
011:384TM1clocks
100:512TM1clocks
101:640TM1clocks
110:768TM1clocks
111:896TM1clocks
ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,which
arethencomparedwiththeinternalcounter'shighestthreebits.Theresultofthis
comparisoncanbeselectedtocleartheinternalcounteriftheT1CCLRbitissetto
zero.SettingtheT1CCLRbittozeroensuresthatacomparematchwiththeCCRP
valueswillresettheinternalcounter.AstheCCRPbitsareonlycomparedwiththe
highestthreecounterbits,thecomparevaluesexistin128clockcyclemultiples.
Clearingallthreebitstozeroisineffectallowingthecountertooverflowatits
maximumvalue.