Rev. 2.50 130 June 22, 2017 Rev. 2.50 131 June 22, 2017
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
Bit3 T2OC:TP2_0,TP2_1Outputcontrolbit
CompareMatchOutputMode
0:Initiallow
1:Initialhigh
PWMMode/SinglePulseOutputMode
0:Activelow
1:Activehigh
ThisistheoutputcontrolbitfortheTMoutputpin.Itsoperationdependsupon
whetherTMisbeingusedintheCompareMatchOutputModeorinthePWMMode/
SinglePulseOutputMode.IthasnoeffectiftheTMisintheTimer/CounterMode.In
theCompareMatchOutputModeitdeterminesthelogicleveloftheTMoutputpin
beforeacomparematchoccurs.InthePWMModeitdeterminesifthePWMsignalis
activehighoractivelow.
Bit2 T2POL:TP2_0,TP2_1OutputpolarityControl
0:Non-invert
1:Invert
ThisbitcontrolsthepolarityoftheTP2_0orTP2_1outputpin.Whenthebitisset
hightheTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.Ithasno
effectiftheTMisintheTimer/CounterMode.
Bit1 T2DPX:TM2PWMperiod/dutyControl
0:CCRP-period;CCRA-duty
1:CCRP-duty;CCRA-period
Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodand
dutycontrolofthePWMwaveform.
Bit0 T2CCLR:SelectTM2Counterclearcondition
0:TM2ComparatorPmatch
1:TM2ComparatorAmatch
Thisbitisusedtoselectthemethodwhichclearsthecounter.Rememberthatthe
StandardTMcontainstwocomparators,ComparatorAandComparatorP,eitherof
whichcanbeselectedtocleartheinternalcounter.WiththeT2CCLRbitsethigh,
thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.
Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfrom
theComparatorPorwithacounteroverow.Acounteroverowclearingmethodcan
onlybeimplementediftheCCRPbitsareallclearedtozero.TheT1CCLRbitisnot
usedinthePWM,SinglePulseorInputCaptureMode.