Rev. 2.50 148 June 22, 2017 Rev. 2.50 149 June 22, 2017
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
Bit3 T1AOC:TP1AOutputcontrolbit
CompareMatchOutputMode
0:Initiallow
1:Initialhigh
PWMMode/SinglePulseOutputMode
0:Activelow
1:Activehigh
ThisistheoutputcontrolbitfortheTMoutputpin.Itsoperationdependsupon
whetherTMisbeingusedintheCompareMatchOutputModeorinthePWMMode/
SinglePulseOutputMode.IthasnoeffectiftheTMisintheTimer/CounterMode.In
theCompareMatchOutputModeitdeterminesthelogicleveloftheTMoutputpin
beforeacomparematchoccurs.InthePWMModeitdeterminesifthePWMsignalis
activehighoractivelow.
Bit2 T1APOL:TP1AOutputpolarityControl
0:Non-invert
1:Invert
ThisbitcontrolsthepolarityoftheTP1Aoutputpin.WhenthebitissethightheTM
outputpinwillbeinvertedandnotinvertedwhenthebitiszero.Ithasnoeffectifthe
TMisintheTimer/CounterMode.
Bit1 T1CDN:TM1Countercountupordownag
0:Countup
1:Countdown
Bit0 T1CCLR:SelectTM1Counterclearcondition
0:TM1ComparatorPmatch
1:TM1ComparatorAmatch
Thisbitisusedtoselectthemethodwhichclearsthecounter.Rememberthat
theEnhancedTMcontainsthreecomparators,ComparatorA,ComparatorBand
ComparatorP,butonlyComparatorAorComparatorPanbeselectedtoclearthe
internalcounter.WiththeT1CCLRbitsethigh,thecounterwillbeclearedwhena
comparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwill
beclearedwhenacomparematchoccursfromtheComparatorPorwithacounter
overow.AcounteroverowclearingmethodcanonlybeimplementediftheCCRP
bitsareallclearedtozero.TheT1CCLRbitisnotusedintheSinglePulseorInput
CaptureMode.