Rev. 2.50 198 June 22, 2017 Rev. 2.50 199 June 22, 2017
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
I
2
C Bus Initialisation Flow Chart
I
2
C Bus Start Signal
TheSTARTsignalcanonlybegeneratedbythemasterdeviceconnectedtotheI
2
Cbusandnotby
theslavedevice.ThisSTARTsignalwillbedetectedbyalldevicesconnectedtotheI
2
Cbus.When
detected,thisindicatesthattheI
2
CbusisbusyandthereforetheHBBbitwillbeset.ASTART
conditionoccurswhenahightolowtransitionontheSDAlinetakesplacewhentheSCLline
remainshigh.
Slave Address
ThetransmissionofaSTARTsignalbythemasterwillbedetectedbyalldevicesontheI
2
Cbus.
Todeterminewhichslavedevicethemasterwishestocommunicatewith,theaddressoftheslave
devicewillbesentoutimmediatelyfollowingtheSTARTsignal.Allslavedevices,afterreceiving
this7-bitaddressdata,willcompareitwiththeirown7-bitslaveaddress.Iftheaddresssentoutby
themastermatchestheinternaladdressofthemicrocontrollerslavedevice,thenaninternalI
2
Cbus
interruptsignalwillbegenerated.Thenextbitfollowingtheaddress,whichisthe8thbit,denes
theread/writestatusandwillbesavedtotheSRWbitoftheSIMC1register.Theslavedevicewill
thentransmitanacknowledgebit,whichisalowlevel,asthe9thbit.Theslavedevicewillalsoset
thestatusagHAASwhentheaddressesmatch.
AsanI
2
Cbusinterruptcancomefromtwosources,whentheprogramenterstheinterrupt
subroutine,theHAASbitshouldbeexaminedtoseewhethertheinterruptsourcehascomefrom
amatchingslaveaddressorfromthecompletionofadatabytetransfer.Whenaslaveaddressis
matched,thedevicemustbeplacedineitherthetransmitmodeandthenwritedatatotheSIMD
register,orinthereceivemodewhereitmustimplementadummyreadfromtheSIMDregisterto
releasetheSCLline.