Holtek HT66F30 - Page 242

Rev. 2.50 242 June 22, 2017 Rev. 2.50 243 June 22, 2017
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
USR Register
TheUSRregisteristhestatusregisterfortheUART,whichcanbereadbytheapplicationprogram
todeterminethepresentstatusoftheUART.AllagswithintheUSRregisterarereadonly.Further
explanationoneachoftheagsisgivenbelow:
Bit 7 6 5 4 3 2 1 0
Name PERR NF FERR OERR RIDLE RXIF TIDLE TXIF
R/W R R R R R R R R
POR 0 0 0 0
1 0 1 1
Bit7 PERR:Parityerrorag
0:Noparityerrorisdetected
1:Parityerrorisdetected
ThePERRflagistheparityerrorflag.Whenthisreadonlyflagis0,itindicatesa
parityerrorhasnotbeendetected.Whentheagis1,itindicatesthattheparityofthe
receivedwordisincorrect.ThiserroragisapplicableonlyifParitymode(oddor
even)isselected.Theagcanalsobeclearedbyasoftwaresequencewhichinvolves
areadtothestatusregisterUSRfollowedbyanaccesstotheRXRdataregister.
Bit6 NF:Noiseag
0:Nonoiseisdetected
1:Noiseisdetected
TheNRflagisthenoiseflag.Whenthisreadonlyflagis0,itindicatesnonoise
condition.Whentheflagis1,itindicatesthattheUARThasdetectednoiseonthe
receiverinput.TheNFagissetduringthesamecycleastheRXIFagbutwillnot
besetinthecaseofasoverrun.TheNFagcanbeclearedbyasoftwaresequence
whichwillinvolveareadtothestatusregisterUSRfollowedbyanaccesstotheRXR
dataregister.
Bit5 FERR:Framingerrorag
0:Noframingerrorisdetected
1:Framingerrorisdetected
TheFERRagistheframingerrorag.Whenthisreadonlyagis"0",itindicates
thatthereisnoframingerror.Whentheagis"1",itindicatesthataframingerror
hasbeendetectedforthecurrentcharacter.Theagcanalsobeclearedbyasoftware
sequencewhichwillinvolveareadtothestatusregisterUSRfollowedbyanaccessto
theRXRdataregister.
Bit4 OERR:Overrunerrorag
0:Nooverrunerrorisdetected
1:Overrunerrorisdetected
TheOERRagistheoverrunerroragwhichindicateswhenthereceiverbufferhas
overowed.Whenthisreadonlyagis0,itindicatesthatthereisnooverrunerror.
Whentheagis1,itindicatesthatanoverrunerroroccurswhichwillinhibitfurther
transferstotheRXRreceivedataregister.Theagisclearedbyasoftwaresequence,
whichisareadtothestatusregisterUSRfollowedbyanaccesstotheRXRdata
register.
Bit3 RIDLE:Receiverstatus
0:Datareceptionisinprogress(databeingreceived)
1:Nodatareceptionisinprogress(receiverisidle)
TheRIDLEagisthereceiverstatusag.Whenthisreadonlyagis0,itindicates
thatthereceiverisbetweentheinitialdetectionofthestartbitandthecompletion
ofthestopbit.Whentheagis1,itindicatesthatthereceiverisidle.Betweenthe
completionofthestopbitandthedetectionofthenextstartbit,theRIDLEbitis1
indicatingthattheUARTreceiverisidleandtheRXpinstaysinlogichighcondition.