Rev. 2.50 248 June 22, 2017 Rev. 2.50 249 June 22, 2017
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
BRG Register
Bit 7 6 5 4 3 2 1 0
Name
BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR × × × × × × × ×
“×” unknown
Bit7~0 BRG7~BRG0:BaudRatevalues
ByprogrammingtheBRGHbitinUCR2Registerwhichallowsselectionofthe
relatedformuladescribedaboveandprogrammingtherequiredvalueintheBRG
register,therequiredbaudratecanbesetup.
UART Module Setup and Control
Fordatatransfer,theUARTfunctionutilizesanon-return-to-zero,morecommonlyknownasNRZ,
format.Thisiscomposedofonestartbit,eightorninedatabitsandoneortwostopbits.Parity
issupportedbytheUARThardwareandcanbesetuptobeeven,oddornoparity.Forthemost
commondataformat,8databitsalongwithnoparityandonestopbit,denotedas8,N,1,isused
asthedefaultsetting,whichisthesettingatpower-on.Thenumberofdatabitsandstopbits,along
withtheparity,aresetupbyprogrammingthecorrespondingBNO,PRT,PRENandSTOPSbitsin
theUCR1register.Thebaudrateusedtotransmitandreceivedataissetupusingtheinternal8-bit
baudrategenerator,whilethedataistransmittedandreceivedLSBrst.Althoughthetransmitter
andreceiveroftheUARTarefunctionallyindependent,theybothusethesamedataformatandbaud
rate.Inallcasesstopbitswillbeusedfordatatransmission.
• Enabling/DisablingtheUART
Thebasicon/offfunctionoftheinternalUARTfunctioniscontrolledusingtheUARTENbitin
theUCR1register.IftheUARTEN,TXENandRXENbitsareset,thenthesetwoUARTpins
willactasnormalTXoutputpinandRXinputpinrespectively.Ifnodataisbeingtransmittedon
theTXpin,thenitwilldefaulttoalogichighvalue.
ClearingtheUARTENbitwilldisabletheTXandRXpinsandthesetwopinswillbeinthe
stateofhighimpedance.WhentheUARTfunctionisdisabled,thebufferwillberesettoan
emptycondition,atthesametimediscardinganyremainingresidualdata.DisablingtheUART
willalsoresettheenablecontrol,theerrorandstatusagswithbitsTXEN,RXEN,TXBRK,
RXIF,OERR,FERR,PERRandNFbeingclearedwhilebitsTIDLE,TXIFandRIDLEwillbe
set.TheremainingcontrolbitsintheUCR1,UCR2andBRGregisterswillremainunaffected.
IftheUARTENbitintheUCR1registerisclearedwhiletheUARTisactive,thenallpending
transmissionsandreceptionswillbeimmediatelysuspendedandtheUARTwillberesettoa
conditionasdenedabove.IftheUARTisthensubsequentlyre-enabled,itwillrestartagainin
thesameconguration.