Rev. 2.50 254 June 22, 2017 Rev. 2.50 255 June 22, 2017
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
UART Module Interrupt Structure
SeveralindividualUARTconditionscangenerateaUARTinterrupt.Whentheseconditionsexist,
alowpulsewillbegeneratedontheINTlinetogettheattentionofthemicrocontroller.These
conditionsareatransmitterdataregisterempty,transmitteridle,receiverdataavailable,receiver
overrun,addressdetectandanRXpinwake-up.Whenanyoftheseconditionsarecreated,ifits
correspondinginterruptcontrolisenabledandthestackisnotfull,theprogramwilljumptoits
correspondinginterruptvectorwhereitcanbeservicedbeforereturningtothemainprogram.Four
oftheseconditionshavethecorrespondingUSRregisteragswhichwillgenerateaUARTinterrupt
ifitsassociatedinterruptenablecontrolbitintheUCR2registerisset.Thetwotransmitterinterrupt
conditionshavetheirowncorrespondingenablecontrolbits,whilethetworeceiverinterrupt
conditionshaveasharedenablecontrolbit.Theseenablebitscanbeusedtomaskoutindividual
UARTinterruptsources.
Theaddressdetectcondition,whichisalsoaUARTinterruptsource,doesnothaveanassociated
ag,butwillgenerateaUARTinterruptwhenanaddressdetectconditionoccursifitsfunctionis
enabledbysettingtheADDENbitintheUCR2register.AnRXpinwake-up,whichisalsoaUART
interruptsource,doesnothaveanassociatedag,butwillgenerateaUARTinterruptiftheUART
moduleiswokenupbyafallingedgeontheRXpin,iftheWAKEandRIEbitsintheUCR2register
areset.NotethatintheeventofanRXwake-upinterruptoccurring,therewillbeacertainperiodof
delay,commonlyknownastheSystemStart-upTime,fortheoscillatortorestartandstabilizebefore
thesystemresumesnormaloperation.
NotethattheUSRregisterflagsarereadonlyandcannotbeclearedorsetbytheapplication
program,neitherwilltheybeclearedwhentheprogramjumpstothecorrespondinginterrupt
servicingroutine,asisthecaseforsomeoftheotherinterrupts.Theflagswillbecleared
automaticallywhencertainactionsaretakenbytheUART,thedetailsofwhicharegiveninthe
UARTregistersection.TheoverallUARTinterruptcanbedisabledorenabledbytherelated
interruptenablecontrolbitsintheinterruptcontrolregistersofthemicrocontrollertodecidewhether
theinterruptrequestedbytheUARTmoduleismaskedoutorallowed.
UART Module Interrupt Structure