Rev. 2.50 60 June 22, 2017 Rev. 2.50 61 June 22, 2017
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
Bit3 LTO :Lowspeedsystemoscillatorreadyag
0:Notready
1:Ready
Thisisthelowspeedsystemoscillatorreadyagwhichindicateswhenthelowspeed
systemoscillatorisstableafterpoweronresetorawake-uphasoccurred.Theag
willbelowwhenintheSLEEP0Modebutafterawake-uphasoccurred,theagwill
changetoahighlevelafter1024clockcyclesiftheLXToscillatorisusedand1~2
clockcyclesiftheLIRCoscillatorisused.
Bit2 HTO:Highspeedsystemoscillatorreadyag
0:Notready
1:Ready
Thisisthehighspeedsystemoscillatorreadyagwhichindicateswhenthehighspeed
systemoscillatorisstable.Thisagisclearedto"0"byhardwarewhenthedeviceis
poweredonandthenchangestoahighlevelafterthehighspeedsystemoscillatoris
stable.Thereforethisagwillalwaysbereadas"1"bytheapplicationprogramafter
devicepower-on.TheagwillbelowwhenintheSLEEPorIDLE0Modebutafter
awake-uphasoccurred,theagwillchangetoahighlevelafter1024clockcyclesif
theHXToscillatorisusedandafter15~16clockcyclesiftheERCorHIRCoscillator
isused.
bit1 IDLEN:IDLEModecontrol
0:Disable
1:Enable
ThisistheIDLEModeControlbitanddetermineswhathappenswhentheHALT
instructionisexecuted.Ifthisbitishigh,whenaHALTinstructionisexecutedthe
devicewillentertheIDLEMode.IntheIDLE1ModetheCPUwillstoprunning
butthesystemclockwillcontinuetokeeptheperipheralfunctionsoperational,if
FSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstop
inIDLE0mode.IfthebitislowthedevicewillentertheSLEEPModewhenaHALT
instructionisexecuted.
bit0 HLCLK:systemclockselection
0:f
H
/2~f
H
/64orf
L
1:f
H
Thisbitisusedtoselectifthef
H
clockorthef
H
/2~f
H
/64orf
L
clockisusedasthe
systemclock.Whenthebitishighthef
H
clockwillbeselectedandiflowthe
f
H
/2~f
H
/64orf
L
clockwillbeselected.Whensystemclockswitchesfromthef
H
clock
tothef
L
clockandthef
H
clockwillbeautomaticallyswitchedofftoconservepower.