Holtek HT66F30 - Page 65

Rev. 2.50 64 June 22, 2017 Rev. 2.50 65 June 22, 2017
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
Entering the SLEEP0 Mode
ThereisonlyonewayforthedevicetoentertheSLEEP0Modeandthatistoexecutethe"HALT"
instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto"0"andthe
WDTandLVDbothoff.Whenthisinstructionisexecutedundertheconditionsdescribedabove,the
followingwilloccur:
• Thesystemclock,WDTclockandTimeBaseclockwillbestoppedandtheapplicationprogram
willstopatthe"HALT"instruction.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheWDTwillbeclearedandstoppednomatteriftheWDTclocksourceoriginatesfromthef
SUB

clockorfromthesystemclock.
• TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownag,PDF,willbesetandtheWatchdogtime-outag,TO,
willbecleared.
Entering the SLEEP1 Mode
ThereisonlyonewayforthedevicetoentertheSLEEP1Modeandthatistoexecutethe"HALT"
instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto"0"andthe
WDTorLVDon.Whenthisinstructionisexecutedundertheconditionsdescribedabove,the
followingwilloccur:
• ThesystemclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopat
the“HALT”instruction,buttheWDTorLVDwillremainwiththeclocksourcecomingfromthe
f
SUB
clock.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheWDTwillbeclearedandresumecountingiftheWDTclocksourceisselectedtocomefrom
thef
SUB
clockastheWDTisenabled.
• TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownag,PDF,willbesetandtheWatchdogtime-outag,TO,
willbecleared.
Entering the IDLE0 Mode
ThereisonlyonewayforthedevicetoentertheIDLE0Modeandthatistoexecutethe“HALT”
instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andthe
FSYSONbitinWDTCregisterequalto“0”.Whenthisinstructionisexecutedundertheconditions
describedabove,thefollowingwilloccur:
• Thesystemclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”
instruction,buttheTimeBaseclockandf
SUB
clockwillbeon.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheWDTwillbeclearedandresumecountingiftheWDTclocksourceisselectedtocomefrom
thef
SUB
clockandtheWDTisenabled.TheWDTwillstopifitsclocksourceoriginatesfromthe
systemclock.
• TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownag,PDF,willbesetandtheWatchdogtime-outag,TO,
willbecleared.