Holtek HT66F30 - Page 72

Rev. 2.50 72 June 22, 2017 Rev. 2.50 73 June 22, 2017
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
Whentheresetpinisdrivenlowbyexternalhardware,mostofthemicrocontrollerpinswillbe
forcedintoahighimpedancecondition.HoweverspecialattentionmustbemadetothePA5/
C1X/SDO/AN5pinwillbeforcedintoalogicaloutputlowconditionandPB2/OSC2pinwillbe
invertedbyPB1/OSC1pinwhentheresetpinisheldlow.Forthisreasonitisrecommendedthat
thesetwopinsarenotconnectedtolowimpedancesourcesintheapplicationcircuittoeliminatethe
possibilityoftwolowimpedancesourcesbeingconnectedtogether.Thissituationonlyoccurswhen
theresetpinispulledlowbyexternalhardwareandnotduringapoweronorotherresettype.
Pin Name Pin Status
PA5/C1X/SDO/AN5 Output Low
PB2/OSC2 Inverted by PB1/OSC1
Other pins High Impedance
• LowVoltageReset–LVR
Themicrocontrollercontainsalowvoltageresetcircuitinordertomonitorthesupplyvoltage
ofthedevice,whichisselectedviaacongurationoption.Ifthesupplyvoltageofthedevice
dropstowithinarangeof0.9V~V
LVR
suchasmightoccurwhenchangingthebattery,theLVR
willautomaticallyresetthedeviceinternally.TheLVRincludesthefollowingspecifications:
ForavalidLVRsignal,alowvoltage,i.e.,avoltageintherangebetween0.9V~V
LVR
mustexist
forgreaterthanthevaluet
LVR
speciedintheA.C.characteristics.Ifthelowvoltagestatedoes
notexceedt
LVR
,theLVRwillignoreitandwillnotperformaresetfunction.Oneofarangeof
speciedvoltagevaluesforV
LVR
canbeselectedusingcongurationoptions.

    
     
Note:t
RSTD
ispower-ondelay,typicaltime=100ms
Low Voltage Reset Timing Chart
•WatchdogTime-outResetduringNormalOperation
TheWatchdogtime-outResetduringnormaloperationisthesameasahardwareRESpinreset
exceptthattheWatchdogtime-outagTOwillbesetto“1”.
     
 
    
Note:t
RSTD
ispower-ondelay,typicaltime=100ms
WDT Time-out Reset during Normal Operation Timing Chart
• WatchdogTime-outResetduringSLEEPorIDLEMode
TheWatchdogtime-outResetduringSLEEPorIDLEModeisalittledifferentfromotherkinds
ofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStack
Pointerwillbeclearedto"0"andtheTOagwillbesetto"1".RefertotheA.C.Characteristics
fort
SST
details.
 
 
    
Note:Thet
SST
is15~16clockcyclesifthesystemclocksourceisprovidedbyERCorHIRC.
Thet
SST
is1024clockforHXTorLXT.Thet
SST
is1~2clockforLIRC.
WDT Time-out Reset during SLEEP or IDLE Timing Chart