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The trace formats are interpreted as follows:
>>CPU instr: S 0002
05757 105736 UJP 2111
Instruction mnemonic
Octal data (instruction opcode)
Octal address (P register)
Octal physical page number
Memory map (system/user/disabled)
>>CPU instr: U 0001
02111 000011 interrupt
Interrupt classification
Octal interrupting select code
Octal address (P register) at interrupt
Octal physical page number at interrupt
Memory map (system/user/disabled) at interrupt
>>CPU data: - 0000 01013 005557 data read
>>CPU data: U 0000 01776 000104 unprotected write
>>CPU fetch: S 0002
05757 105736 instruction fetch
Memory access classification
Octal data (memory contents)
Octal logical address (effective address)
Octal physical page number
Memory map (system/user/disabled)
>>CPU reg: P **** 01011
042200 A 177777, B 177777, X 177777, Y 000000, e O I
Register values and interrupt system status
S register
MEM base-page fence register
Protection status (protected/unprotected)
>>CPU reg: - **** ***** ****** MPF 000000, MPV 002111, MES 163011, MEV 030000
MP and MEM register values
Protection status (protected/unprotected)
>>CPU opnd: * **** 20056 105251 virtual address 1400006
>>CPU opnd: * **** 20056 105251 dimension 1 element count 1024
>>CPU opnd: * **** 20056 105251
element size 2 offset 00000000000
Instruction-specific operand value
Associated instruction opcode
Octal address (P register)
>>CPU instr: - 0001
02200 102077 simulation stop: Programmed halt
Reason for the simulation stop
Octal data (T register)
Octal address (M register)
Octal physical page number
Memory map (system/user/disabled)
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