28
Enabling CPU tracing can produce a very large number of lines very quickly, so care should be used to enable
tracing only around the area of interest. Breakpoint actions may be used to implement this; for example:
BREAK 100; SET CPU DEBUG; GO
BREAK 200; SET CPU NODEBUG; GO
These commands will enable tracing when the program counter reaches location 100 and disable tracing when it
reaches location 200, thereby producing a trace of instructions executed between locations 100 and 200.
Alternately, if the execution of specific instructions is of interest, the EXEC trace option may be used to reduce the
debug log file size.
3.1.5 Registers
The CPU state contains the registers visible to the programmer and the interrupt and dynamic mapping system
control registers:
Name Size Radix Symbolic Read-Only Description
P
15 8 Program Counter
A
16 8
Accumulator A
B
16 8
Accumulator B
M
15 8 Memory Address Register
T
16 8
Memory Data Register
X
16 8
Index Register X
Y
16 8
Index Register Y
S
16 8
Display Register
E
1 2 Extend Register
O
1 2 Overflow Register
CIR
6 8 Central Interrupt Register
ION
1 2 Interrupt System Enabled
ION_DEFER
1 2 Interrupt Deferred
DMSENB
1 2 MEM Enabled Flag
DMSCUR
1 2 User Map Selected Flag
DMSSR
16 8 MEM Status Register
DMSVR
16 8 MEM Violation Register
DMSMAP [0:127]
16 8 MEM Map Registers
IOPSP
16 8 I/O Processor Stack Pointer
PCQ [0:63]
15 8
Program Counter Queue
The A, B, T, X, Y, and S registers may be examined or deposited using any of the modes described in the Symbolic
Display and Entry section above.
3.2 12578A/12607B/12895A Direct Memory Access Controllers,
12897B Dual-Channel Port Controller
Direct memory access controllers permit the computer to transfer data directly between an I/O device and memory
on a cycle-stealing basis. Depending on the CPU, the device interface, and main memory speed, DMA is capable
of transferring data blocks from 1 to 32,768 words in length at rates between 500,000 and 1,000,000 words per
second.
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