HP 4262A User Manual

Section VIII
Paragraphs 8-21 to 8-27
8-21. BLOCK DIAGRAM DISCUSSION.
8-22. Analog Section Discussion.
These paragraphs describe how each individual cir-
cuit section operates to establish L, C, R and D
measurement values as controlled by the digital
section. Figure 8-6 is a schematic block diagram of
the 4262A analog section. The table in Figure 8-6
shows the range and source resistor values selected
by range and function controls.
8-23. A11 Oscillator and Source Resistor.
The test signal is generated by an amplitude stabi-
lized Wien Bridge type oscillator. Oscillator output
is fed through an attenuator (A11R18 and R19) to
a power amplifier. Attenuator switch A3Q3 tums
on only when a Cp measurement is being made and
the TEST SIGNAL LOW LEVEL button is pushed.
The oscillator signal from the secondary of trans-
former T2 is designed to have a low output imped-
ance via source resistor Ro to the unknown device
(Cx in diagram). Transformer T2 isolates the power
amplifier from dc bias voltages which can be appli-
ed to unknown device. The A11 Board includes an
L Offset Control circuit which provides a compen-
sation circuit to compensate for residual induct-
ance of test leads or fixture. The operating princi-
ple g_f4 the L Offset Control is diagrammed in Fig-
ure 84.
8-24. The unknown connection is basically a four
terminal (five terminals including GUARD terminal)
configuration method. The GUARD terminal is
connected directly to the instrument chassis. Cir-
cuit common for all PC boards is also eventually
connected to the chassis. DC bias voltages up to
+40 volts (+6V internally) can be applied to un-
known device. The DC bias circuit is illustrated in
Figure 8-5.
8-25. A12 Range Resistor.
The current that flows through Cx also flows
through range resistor Rr. The range resistor ampli-
fier causes the voltage across Rr to represent (ex-
actly) the current flow through Cx. Ro and Rr are
selected by a range control signal from the digital
section. The table in Figure 8-6 describes how the
resistors are controlled. C Offset Control circuit is
capable of compensating for stray capacitance up
to 10pF (see Figure 8-4 for operating principle).
8-26. A13 Process Amplifier.
The very precise voltage across Cx and Rr are
fed to differential amplifiers (A13U1 through U4.C2
and C4 are dc blocking capacitors. This assembly
processes these signals to feed the €ref signal (re-
ference phase signal used for phase detection) and
the €m signal (signal measured by the integrator)
to the A6 board. The two input signals are selected
according to specific measurement rules and are
used as €ref and €m signals. The @ref signal is
chosen at the same time that the measurement cir-
88
Model 4262A
cuit mode is selected. Setting the CIRCUIT MODE
to PRL selects the voltage across Cx as the €ref
signal. When the CIRCUIT MODE is set to SER,
the voltage across Rr is selected as the €ref signal.
In the AUTO measurement mode, the €ref signal
selection is done automatically and applied in a
manner similar to the above. The selected €ref
signal is amplified by A13U5A and is wave-shaped
by A13U5B and U7 which also adjusts the phase
angle of €ref by a control input (APAO signal)
from A1l4 Board.
The €m signal is selected by FET switches A13Q2,
Q3, Q5, and Q6 which are, in turn, controlled by
signal selection signals from the digital section. The
method of selecting the €m signal is graphically
shown in Figure 8-8 Timing Diagrams. The selected
€m signal is amplified by A13U6A, U6B and
becomes an input signal for the phase detector on
Al14 Board. The switches A13Q19 and Q18 tumn
on and off respectively to interrupt the €m signal
flow during integrator offset control period. When
TEST SIGNAL LOW button is pushed and lights
(this pushbutton functions in Cp measurement
mode only), the gain of amplifiers A13USA and
U6B is increased. Thus, the voltage levels of €ref
and €m signals remain the same as when making a
measurement at the nominal (high) test signal level.
An SAT detector detects any €m signal level that
exceeds approximately 5 volts and transfers such
SAT signals to digital section.
8-27. A14 Phase Detector and Integrator.
The Al4 Board consists of three major circuit sec-
tions: PLL Reference Phase Generatar, Phase De-
tector,and Integrator. The specific end functions of
the two input signals, €ref and €m are to establish
a ZERO signal whose time interval is equivalent to
the desired measurement quantity. This ZERO
signal is fed to A23 Board to be manipulated by
the nanoprocessor.
The Reference Phase Generator produces four re-
ference phase signals each being different by 90
degrees in phase one from the other (these four
signals are phase shifted respectively 0, n/2, # and
3m /2 in radius vector as referred to the input signal
€ref.). The reference phase signals are individually
selected in a manner peculiar to the measurement
modes (four types). The selected reference phase
signal is fed to the Phase Detector to drive switch-
es A14Q19, Q20, Q22 and A23 of the Phase De-
tector. The method of selecting the reference phase
signal is illustrated in Figure 8-8 Timing Diagram.
To establish the very accurate 90° phase difference,
the Reference Phase Generator employs a Phase
Locked Loop (PLL) circuit consisting of a local
phase detector (PD), filter, and voltage controlled
oscillator (VCO). Thus measurement error is mini-
mized. An explanation of Reference Phase Genera-
tor operation is given on Service Sheet 14.
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HP 4262A Specifications

General

Brand	HP
Model	4262A
Category	Measuring Instruments
Language	English