HP 4262A User Manual

Section VIII
Paragraph 8-34
8-34. TIMING DIAGRAM DISCUSSION.
8-35. Figure 8-8 presents a timing diagram for the
4262A. The upper part of the diagram shows out-
put
waveforms
of
the
integrator,
execute
time
for
each measurement sequence, and main control
signals which direct the vector voltage ratio meas-
urement. As may be seen from the diagram, the in-
strument first measures the L/C or R value and
then the dissipation (D) and Q (calculated from D)
factors. Approximately three seconds after the
LINE switch is depressed to turn the instrument on,
power voltage (V&) is applied to the nanopro-
cessor through a delay switch (A23 board). The
nanoprocessor is simultaneously set to its initial
conditions ready for beginning the display test
which precedes measurement. When the display
test ends, the processor sets the 4262A to a pre-
determined measurement mode (automatic initial
settings) and a capacitance measurement is ini-
tiated. When LCR and DQ ranges are set to AUTO,
the autoranging recycle repeats until an LCR range
suitable for the sample is selected. A front panel
range indicator lamp lights and step-shifts to left or
right. The displays show blanking signs (- - -)
during autoranging period. If the sample is too
large (in PRL mode) or too small a
value (in SER mode) compared to the range, the
Saturation Detector (A13) send a SAT signal to the
nanoprocessor. Range is shifted just after Offset
Null operations are completed (instrument does
not cycle through steps in remaining measurement
sequence). This permits faster ranging. Setting LCR
RANGE to MANUAL bypasses autoranging cycle.
When a range is selected in which integrator dis-
charge time interval is within 162 and 1820 clock
periods (limits), the measurement sequence pro-
ceeds with an L/C/R measurement cycle. To mini-
mize vector voltage ratio measurement error, Off-
set Null and Auto Phase Adjustment sequences pre-
cede integrator charge/discharge (by phase detect-
ed DUT signal). During Offset Null period, A13Q19
tums on and Q18 turns off to interrupt the em
signal transfer. At this time, any output of the in-
tegrator caused by residual phase detector output
voltage and integrator output offset voltage is fed
back to the input of the integrator to reduce the
output of the integrator to zero. And this feedback
voltage is stored in a memory capacitor during the
measurement to eliminate any measurement error
8-12
Model 4262A
due to residual phase detector and integrator volt-
ages. Refer to service sheet 14 for offset null con-
trol details.
At each integrator operating sequence change, a
HOLD TIME is provided to prevent a switching
transient waveform from entering the integrator
and/or to permit full discharge of the integrator
capacitor (from previous integrator operation).
Now, an Auto Phase Adjustment consisting of two
periods begins. During these periods, to minimize
measurement error, the phase detector phase refer-
ence is precisely set. APA1 (Auto Phase Adjust-
ment 1) and APAZ2 . control signals administer
switches A14Q13, Q14 and Q15 timing to accom-
plish phase adjustment of €ref signal (A14TP1) for
establishing exact detection phases of Phase De-
tector. The Integrator disregards this phase adjust-
ment sequence. Refer to service sheet 14 for auto
phase adjustment details.
When an integrator charge period is initiated, the
DUT signal (synchronously phase detected) is ap-
plied to the integrator input. The Integrator is
charged with the incoming signal (dc) for a con-
stant time interval (see table in timing diagram).
Two kinds of integrator waveforms are developed
depending on measurement function and circuit
mode. In the Cp measurement mode, integrator
output voltage is increased as its charge is propor-
tional to the DUT current (voltage across Rr) and
is decreased as its discharge is proportional to
the (constant) voltage across the DUT (constant
decay rate). On the other hand, in the Cs
measurement mode, the integrator rapidly charges
in a short time — the constant voltage across Rr
representing the current flowing through the DUT.
The integrator discharge depends on the voltage
across the DUT (and is proportional to DUT). De-
tailed integrator operation peculiar to each meas-
urement mode group is described in ‘Principles of
Operation” on Page 8-4. The nanoprocessor
counts the time of a 31.83kHz (10000/r kHz)
clock for the time required to discharge the in-
tegrator until integrator output voltage reaches the
zero level. When integrator output voltage crosses
the zero level, a zero detector transfers the ZERO
signal to the nanoprocessor. The Nanoprocessor
stops counting and stores a number corresponding
to the L, C or R value of DUT in its internal
registers.

HP 4262A Specifications

General

Brand	HP
Model	4262A
Category	Measuring Instruments
Language	English