HP 4262A User Manual

Model 4262A
Successively, the D measurement cycle begins. The
D autoranging recycle is done or repeats once to
set instrument to appropriate D range. After an
offset null sequence for D measurement, the
integrator begins to charge — its incoming voltage
being proportional to the conductance or resist-
ance of the DUT. Discharge time is proportional to
the reactance of the DUT. To calculate the ratio of
the real to the imaginary part of the DUT current
(voltage across DUT when circuit mode is SER),
the integrator is charged when the detection
phase of the detected output is at “90”
degrees. In R measurements, the D measurement
cycle is omitted. Since the electrical response time
for each measurement frequency is different and
the charge cycle time is sometimes a function of
this frequency, the sequence execute times are
different for measurement frequencies of 120Hz,
1kHz and 10kHz. Note that the execute time for
the discharge sequence is variable.
8-36. The table shown in the lower part of the
diagram explains how voltage Em is selected by the
instrument (either from voltage across Rr or the
voltage across the UNKNOWN) and how the de-
tection phase for the phase detection, employed in
either PRL and SER circuit modes, is selected.
Both upper and lower sections of the waveform
timing diagram have the same time scale. -€x,
-€x/10, -ey and -€y/10 in the €m column are
names for voltages shown in diagram Note 2.
Diagram Note 3 shows the phase relationships of
the voltages applied to phase detector FET
switches A14Q19, Q20, Q22 and Q23 (detection
phase) along with the phase of €ref signal at A14
TP5. The detection phase is sequentially selected
by PHASE control signals (¢~3n/2) which are
transmitted to 4 Phase Selector on Al4 board
(from A23 Nanoprocessor & ROM board).
Note
Labels H1 through H10 in the tim-
ing diagram denote the timing for
trigger used when troubleshooting
instrument using A23 service board
(service kit 04262-87001). The
4262A measurement sequence can
be stopped at or resumed from the
desired point from among these
triggering points by pushing specific
4262A front panel buttons.
Note
1.
Unit
for
excute
time
is
msec
except
for
discharge
sequence.
Note
2.
Selection
of
€p.
"
EvL
N
E2
\
Ro
r)I
ki
:\
Rg
/
)
v
N
-
a—
v
em
VSEL
1*
|
VSEL2*
-ex
0
0
- ey
1
[}
-ex/10
0
1
ey/10
1
1
* Gating signals for
Al3 FET switches.
Note 3. Phase for Phase Detector
err _ [ L[ L[ L
(A14TP5)
(N
Gy
U
/2 e Rl EEEEE
Note 4. When dissipation factor range is 20,
the -€x and -y are attenuated by
1/10.
Section VIII
Figure 8-8
r
MEASUREMENT
CYCLE
w
s
L/C/R
MEASUREMENT
D/Q
MEASUREMENT
E—
\PPED OVER THIS PERIOD
—
o
LCR
AUTO
RANGING
RECYCLE
—
e
S
RtuErT
UNCAL
G
AUTORANGING
RECYCLE
——
—
INTEGRA’)TOR
OUTPUT
=
(AI4TPI
-
_
o
w
3
3
g5
4=
g
Y
3
.
¥
3
z
of
TW
$&
o
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o
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=
o
o
o<
c
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Jaz
as
)
z
J
I
[
r}
4
|
x
o
[
o
AF
=
o
o
o
L
o
<
oo
I
Il
ow
Oow
T
I
(Lh>
(7]
I
I
I|o
K_’
s
ED
E3
FUNCTION
8
CKT
MODE
12
u
S
=
v
i
%
aad
a
o
S
O32,5/count
©
Excute
Time*'
|KHz
o
<li<0l
42
Cp,LsiCs,Lp|
Rs
|
Rp.
o
S
A
N\
FREQUENCY
|OKH2”
37ms
IRE
30
11501
S
1321
3
PN
37,5
count
T7mb
3
32
6
30ms
120Hz
To0mS
125
240
42)
5
132)
3
Paa"
3zus/count
loonis
%4
32
T
30mS
32uS/count
RESET (A23 SL) -u
OFFSET NULL
(A23pin
IL)
I
APA | (A23 pinAL)
APA 2 (A23pin2L) :
STN (A23pin3L) :
SAT (AI3pin9R) :
|
e
1
i
)
!
11
!
{H1
H2
H3
H4
H5
HE
H7
H8
HO
HIO
|
I
I
-
] £7 -€
»2]
Ls
—ex
I
~€y/10
|
-ex
~ey/10
|
-€x
—oX
Ls,
Cp
|
Cp
%
-y
|
-ex/10
]
-€y
~ex/10
|
-ey*1
I
ey
Ehose
tor
Prass
|
e
2’
2
|
}
-
-ex
»2|
Cs_1
-€X
I
-ey/10
ex*4
—
Lp,Cs|
€m
[Tp
|
ey
I
~ex/10
—ey*4
ey
rors
for
e
|
”
I
o
"
j————— =
|
Rs
em.’ZI
Rs
|
-€x
I
-ey/10
-ex
I
-ey/10
e
sl
/2
[
S
U
"
___
|
Rp
em'zl
Rp
:
-ey
|
-ex/10
l
-ey
-ey
Phase
for
Phase
|
7/2
|
7
|
I
w2
Detector
e
e
—E———,—
T
T
T
T
T
T
T
T
T
T
T
T
T
Figure 8-8. Timing Diagram.
8-13

HP 4262A Specifications

General

Brand	HP
Model	4262A
Category	Measuring Instruments
Language	English