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HP 4262A - Page 232

HP 4262A
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A13
BOARD
CIRCUIT
DESCRIPTION.
The
input
circuitry
of
the
A13
board
is
composed
of
impedance
converters
and
differential
amplifiers
which
sense
the
exact
voltage
drops
across
the
DUT
(E1)
and
across
range
resistor
(E2).
The
choice
of
the
€ref
and
Em
signals
by
Q1
through
Q6
depends
upon
the
FUNCTION
and
CIRCUIT
MODE
settings.
Switches
Q1
and
Q4
select
the
phase
detector
phase
references
(€ref)
from
either
€x
or
€y
(representing
E1
and
E2,
respectively)
differential
amplifier
outputs
as
directed
by
the
CMS
(Circuit
Mode
Selection)
signal.
Switches
Q2,
Q3,
Q5
and
Q6
sequentially
select
the
€m
signal
(as
components
of
the
measured
quantity)
from
among
the
€x,
€x/10,
€y
and
€y/10
signals.
The
method
of
the
selection,
relative
to
the
measure-
ment
mode,
is
graphically
illustrated
in
Figure
8-8
Timing
Diagram.
When
the
TEST
SIGNAL
function
is
set
to
LOW
LEVEL,
both
Q16
and
Q17
turn
on.
To
maintain
the
amplitudes
of
€ref
and
€m
signals
the
same
as
in
taking
a
measurement
with
a
standard
test
signal
level,
the
amplification
factors
of
amplifiers
USA
and
U6B
are
now
increased
by
20
times.
If
the
amplitude
of
U6B
output
(€m)
exceeds
+5.2V
peak,
the
window
comparator
U8
outputs
a
SAT
(saturation)
pulse
which
signals
that
an
improper
FUNCTION
or
RANGE
setting
is
being
attempted
for
measuring
the
unknown
device.
Switches
Q18
and
Q19
operate
during
the
integrator
null
offset
sequence
(refer
to
Page
8-56
for
the
null
offset
control
details).
An
APAO
(Auto
Phase
Adjustment
Output)
signal,
added
to
the
€ref
signal
at
the
input
stage
of
the
Phase
Shifter
U5B
causes
a
change
in
the
phase
of
the
€ref
signal.
This
phase
change
on
the
APAO
voltage
is
determined
by
a
comparison
of
the
phase
shifter
output
to
the
zero
level.
Circuit
operating
theory
of
the
Phase
Shifter
is
given
in
the
following
paragraph.
AUTO
PHASE
ADJUSTMENT
(Phase
Control).
This
paragraph
should
be
read
along
with
the
general
description
of
the
auto
phase
adjustment
(on
service
sheet
14).
A
DC
input
(APAO)
to
the
Phase
Shifter
is
added
to
the
ac
input
signal
(€ref)
for
the
purpose
of
shifting
the
ac
waveform
up-
wards
or
downwards
depending
on
the
dc
input
level
(as
illustrated
in
Figure
A).
Additionally,
the
phase
shifter
reverses
polarity
of
the
signal.
The
phase
shifter
output
is
wave-shaped
to
a
square
wave
which
changes
its
polarity
every
time
that
the
phase
shifter
output
waveform
crosses
the
zero
level.
The
waveforms
drawn
in
solid
lines
in
Figure
A
are
those
that
exist
when
OV
dc
input
(APAO)
is
applied.
Waveforms
in
dotted
lines
are
those
that
are
present
when
a
plus
dc
input
(APAO)
is
applied.
When
an
ac
signal
with
a
certain
dc
(APAO)
level
is
inputted,
the
duty
factor
of
the
€ref
signal
is
shifted
(narrowed
or
widened)
as
the
phase
shifter
output
is
wave-shaped
with
respect
to
a
fixed
(0V)
reference.
Therefore,
the
phase
of
the
PLL
output
used
for
phase
detection
will
vary
since
the
PLL
circuit
detects
only
the
trailing
edge
of
an
€ref
signal.
©
AC Input
ogxcsson
fifl
i
-
WAVE
GENERATOR
i
s
Y@
[PHAPER
feref|
o)
L)
OC
input
(
APAO)
€m
4
PHASE
'-
sertrn
—f
[
1
oUTPUT
i
(ONE
OF
--TTe
———
FOUR)
L3
Figure
A.
Phase
Control.
8-52
-

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