HP 4262A - Page 247

A23 PROCESSOR & ROM
+9V DELAY
INITIAL SWITCH
RESET
!
'
30bit
DSR/DSW
RESET
[PROGRAM
ADDRESS
BUS
:
—_——
NANO
»
1IN
ENA
DEVICE
To
Op.
SELECT [
PROCESSOR | DEVICE SELECT cooe') DECODER
PROGRAM CONTROL prey To A2
CLOCK i :
ROM 4096 X8 Ui U3 DSW
uis
U6
—
U4:0SR
To
A22
8BIT DATA BUS LINE
11
OPT SELECT SW
HP 1B |
DATA BUS DRV/REC
cmp |3 g
! 8D |OO fro
I LR |3 us us |
Ij! g |
(=]
x
s
ANALOG SECTION g
CONTROL REGISTER
[,
U7z us Ul 9
@
o 5
vYVYYTYY N
3 y CLOCK
< 4 oo W 1.27 MHz
w [PY R
T w @ ® o
ton ; < w O ; ¢
o 8 2T 8 & 8o 31.83KHz
S4h 9223 EBE&E. <
g O > ¢« o o» - N N had
Figure A. A23 Processor & ROM Block Diagram.
8-62
Nt