APPENDIX
9.4
VER.V09F
NSC800 MACHINE CODE
INSTRUCTION
cz\sNH
AODA,s;ADCA,s t l V I O I
SUBs;SBCA,s,CPs,NEG I I V I 1 I
ANDs
ORs; XOR s
INCs
DEC m
AODDD,n
AOC HL, u
SBC HL, n
RLA,: RLCA. ARA, ARCA
RL
m; RLC m; RR m; RAC m
SLAm;SRAm;SRLm
RLD, ARD
DAA
CPL
SCF
.
I
.
I
I
.
I I
.
I
I I
1 •
0 1
0
0
V I 0 I
V
I
1
I
0 X
V
I
0 X
V
I
1 X
0 0
p
I
0 0
p
I
0 0
p
I
.
I
SECTION 9.4
COMMENTS
8-bi1 add or add with car~y
8-bit subtract, subuac1 with
carry, compare and
negate accumulator
Logical operations
And seu different flags
8-bit increment
8-bit decremenl
16-bit add
16-bit add with carry
16-bit subtract with carry
Rotate accumulator
Rotate and shih locations
Rotate digit left and right
Decimal adjus! accumulator
Complement accumulator
Set carry
CCF
I •
0 X Complement carry
INr, (Cl
• I
P I O O Input reginer indirect
INI; INO; OUTI; OUTO
\NIA; \NOR; OTIR; OTDR
LOI, LOO
• I
• 1
: :
~
: } ~l~c: i~n:u; ~n:t~~::~s: z " 1
LOIA, LDDR
•XIXOO
•xoxoo
Block transfer instructions
P/V
~
1 if BC F 0, otherwise
P/V" 0
CPI, CPIR, CPD, CPOR
• I I X 1 X Block search inst.ructions
LDA,l;LDA,R
BITb,s
NEG
• I IFF t O 0
• I X X O 1
I I V I 1 I
Th, following notllion i1 und in thi1 table:
SYMBOL
OPERATION
z,, 1 ii A" {Hll,
otherwise z,,O
P/V:lifBCF-0,
otherwise P/V " 0
The content of the interrupt
enable flip-flop (IFF)
is
copied inlo !he P/V flag
The complemenl of bi1 b of
location is copied into !he
Z flag
Negale accumulator
C Carry/link flag. C•l if th1 optration produc1d I carry from the MSB of the operand or rtsult.
Z Zero flag. 2•1 if the r11ult of the operation i1 zero.
S Sign flag.
s .. , if the MSB of tht mull is one.
P/V Parity or overflow flag. Parity tPJ and ovuflow
!VI share the same !lag. logical operations
affect this flag with the parity of the result while arithmetic operations affect thil flag with
the ovtrflow of the r11ult. If P/V hold1 parity, P/V"'l if the ruu1t of the operation
is nen,
P/V=O if ruult is odd.
If P/V hold1 overflow, P/V"'1 if the rnult of the operation produced
anorerflow.
Half-carry flag. H .. 1 if the add o, 1ub1rac1 operation
produced a carry into or borrow from
bit 4 of the accumulator.
Add/Subtract flag. N=l if the previous operation was a subtract.
Hand N flags art u11d in conjunction with the decimal adjun inttruction IOAAI to properly
correct the ,uult into p;icked BCD format following addition or subtraction u1ing operands
with p;icked BCD format.
The flag is affected according to the result of the operation.
The
11111 is unchanged by the operaiion.
0 The
11111 i1 rnet by the operation.
1 The flag
is Mt by th1 operation.
X The flag it 1 "don't care."
V P/V flag affected according to the overflow result of the operation.
P PN flag affected according to the parity result of the operation.
Any one of the CPU registers A, B. C, D, E, H,
L.
Any 8-bit location for all the addrening modes allowed for the particular instruction.
Any 16-bit location for all the addreuing modes allowed for that instruction.
Any one of the two inde11 registers IX or IV.
Refresh counter.
8-bit value in range <O, 255>.
16-bit value in range <O, 65535>.
Any 8-bit location for all the addressing modes allowed for the particular instruction.
SUMMARY OF FLAG OPERATION
lslzlxlH!xlPtv!N!cl
Sequence of flags in F register
PAGE 9-7
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