IBM System/360 2050 User Manual

SUPERVISORY CONTROLS
The supervisory controls are the hardware circuits
that determine the CPU control status and the gating
(or blocking) of certain clock pulses within the sys-
tem (Figure 19). These circuits can be divided into
two logical groups.
1. Clock gating control circuits:
a. Circuits to recognize conditions that
require the stopping of one or more
logic clocks.
b. Four clock stop triggers that block or
gate the basic reg and late reg pulses
within the system.
2. CPU control status circuits:
a. Circuits that recognize the need for, and
request a change in CPU control status.
b. A log trigger and three CPU control mode
triggers that determine the CPU control
status.
Clock Gating Control Circuits
There are two main types of clocks in the CPU:
free-running. and non free-running (Figure 20). The
free-running clocks are latch, error, basic reg, and
basic late reg. The non free-running clocks are
CPU-1/0, ROS, and main storage.
The non free-running docks are controlled by
four clock stop triggers. These clock stop triggers
are set/reset latches. Any condition that requires
the blocking of a clock pulse(s) will turn on one or
more of the following clock stop triggers:
l. CPU-I/O clock stop trigger -- When on, this
trigger blocks the reg and late reg pulses to CPU
circuits (regs and counters) and the common channel
circuits.
2. ROS clock stop trigger -- When on, this
trigger blocks the reg and Late reg pulses that set
and reset ROSDR and ROAR. (This effectively stops
ROS.)
3. Main storage clock stop trigger -- When on,
this trigger blocks the reg and late reg pulses that
are used to generate a storage select from CPU,
set IAR, and set SAR.
4. Storage holdoff clock stop trigger -- When
on, this trigger serves the same function as the
CPU-I/O clock stop trigger within CPU but does not
block clock pulses to the common channel. -
One way (of many) to stop the non free-running
clocks is as follows:
1. The FLT load request trigger on, not start,
and not sequence counter mode; brings up the nor-
mal interrupt line.
2. Normal interrupt turns on the main store,
ROS, and CPU-I/O clock stop triggers.
3. The clock stop triggers, in turn, prevent the
indicated clock pulses from occurring.
When all conditions needed to restart a clock are
present, a reset to the clock stop trigger is generated.
CPU Control Status Circuits
The supervisory controls determine and set the CPU
control status triggers. These are sequence counter
mode, main store mode, and ROS mode triggers,
and also the log trigger. These triggers disable
controls that should not be in command and enable
other controls to manipulate identical data paths.
Note that this is not a priority function in the sense
that one set of controls is caused to wait while
another set performs a function.
Changing CPU Control Status
Changing the CPU control status generally involves
a three-step sequence.
1. A supervisory interrupt condition turns on
the clock stop triggers.
2. One dead cycle is then taken. During this
dead cycle, a line Labled "gate status" is used to set
or reset the CPU control status triggers.
3. The logic clocks needed for the newly selected
CPU mode have their clock stop triggers turned off.
A typical example, showing how the CPU control
status is changed, is shown in the following logout
sequence. Refer to TIM 209 (Sheet 1) and Figure 21.
When a logout operation is initiated, the error inter-
rupt line turns on the CPU-I/O, ROS, and MS clock
stop triggers, thus freezing all registers. The next
machine cycle has its non free-running reg and late
reg pulses blocked, and is thus called a dead cycle.
During this dead cycle, the log and sequence counter
mode triggers are set on with a basic regpulse.
During the same dead cycle, the MS clock stop trig-
ger is reset off at error reg time. Starting with the
next machine cycle, the contents of SDR, SAR, and
IAR are stored in locations 80, 84, and 88. Next,
a call for MS mode is initiated. This resets the
sequence counter mode trigger off and sets the MS
mode trigger on. After the storing of ROSDR
(groups 1-4) and ROAR, the ROS clock stop trigger
is reset off, thus allowing the ROS clock to run.
During the next two cycles a call for ROS mode
is initiated. This turns the MS mode trigger off,
sets the ROS mode trigger on, and then resets all
clock stop triggers off.
Supervisory Interrupts
The clock stop triggers and the CPU control status
triggers make up the output interface of the super-
visory controls (Figu.re 19). This interface is nor-
mally in a steady state. The output interface changes
Maintenance Features (3/71) 35

IBM System/360 2050 Specifications

General

Brand	IBM
Model	System/360 2050
Category	Computer Hardware
Language	English