ILLUSTRATIONS
Figure
Title
Page Figure
Title
Page
DIAGNOSTIC TECHNIQUES
so
Model
SO
Diagnostics.
7S
1
Status
of
Indicators
after
System
Reset
11
2 ECAD Block Key 12
PREVENTIVE MAINTENANCE
3
ALO
Page Key • 13
Sl
Model
SO
Preventive
Maintenance
Schedule
79
4
CAS Logic
Diagram
Page Key
14
SERVICE CHECKS, ADJUSTMENT AND REMOVAL
PROCEDURES
MAINTENANCE FEATURES
Service
Checks--CPU
and
Channel
s
Controls,
Latches,
Etc.,
Used
in
S2
Waveform
Measurements
80
Maintenance
Operations
• 18
S3
Main
Storage
Test
Points
81
6
Basic
Operations
and CPU
Control
Modes 19
S4
Main
and Bump
Storage
Addressing
82
7
CPU
Control
Modes for
Maintenance
Operations
19
SS
Main
Storage Strobe
83
8
MS
Mode Instructions
and
Data
Paths.
20
S6
Card
Extender
Jumper
Wire
83
9
Sequence
Counter
Logic
Chart
• 21
S7
Delay
Line
Clock
83
10
F1..
T Op Reg Instructions •
22
S8
Input
to
Delay
Line
Driver
84
11
Scan/Log
Decoder.
22
S9
M9/M9A
Drive
System
84
12
Scan-Out/Logout:
Locations and
Data
(4 Parts)
23
60
Physical
Layout
of
M9/M9A
Planes
8S
13
Scan-Out/Logout:
Logic
and
Indicators
27
61
X
Drive
CuITent
8S
14
ROS Kernels
(Maintenance
Routines)
28
62
Y
Drive
CuITent
8S
lS
ROS Kernels Flowchart:
Diagnose/FLT/
63
Shorted X Drive Line
8S
Log
Trigger
Entl'ies
(2
Parts)
29
64
Open
X Drive Line
86
16
Hardware
Addresses No. 1 and 2 31
6S
Possible Shorted Drive Line
86
17
Storage
Locations
and
Bits for L
Register
~gout
31
66
Possible Open Drive Line
86
18 Logout Under
Sequence
Counter
and
Main
Store
67
Drive
Line Shorted
to
Ground
86
Mode
(2
Parts1 •
33
68
CUITent
Turned
Off by
Terminator
Gate •
87
19 Supervisory Contl'ols
(2
Parts) 37
69
Blue-White
Sense Lines,
Sense-Inhibit
87
20
Clock
Distribution.
39
70
lnhi
bit
Pulse
87
21
Changing
CPU Contl'ol Status 39
71
Inhibit
Pulse with Open Leg
87
22
Diagnose Usage (Scope Bump Word)
41
72
Inhibit
Pulse with Grounded
Sense-Inhibit
Line
or
23
FLT
Tapes:
Model
SO.
41
Shorted
Inhibit
Driver
88
24
FLT
Disk Packs:
Model
SO
41
73
Output
of
Good Sense
Amplifier
(M9
Only)
88
2S
FLT Load
via
Tape
43
74
Main
Storage
Select--W
aveform
88
26 FLT Load
via
Disk
44
7S
Main
Storage
Terminator--Waveforms
88
27
Mask and Expected Response Examples
47
76
Main
Storage
Gate
and
Driver
Patterns--Waveforms
89
28
!vlS
Mode ROS Bit
Test
48
77
Main
Storage Driver
Failures--Waveforms
89
29
Hardcore
Test
Sample:
ROS
Mode
(2
Parts)
49
78
Stl'obe for Each
Segment
and Bit
89
30
F1..
T Load
to
Cycle
Tests
Sl
79
M9A
Suobe
and Sense
Circuits
90
31
FLT
Cycle
Test.s: Word
Format
S2
80
M9A
Preamplifier
Outputs--Waveforms
91
32
F1.T
Zero/One-Cycle
Tests •
S3
81
Local
Storage Address Bit Functions 92
33
FLT
Compare
and Branch
Kernel
S4
82 Extender Card Wiring:
LS
Temperature
Check
• 93
34
FLT
Run and
Repair
Procedure •
SS
83
LS
Write Driver 94
3S
Cycle
Test
Repair
Procedure
S6
84
LS
Bit Driver 94
36 FLT
Scan-In,
Parity
Generation,
and
Scan-Out
60
8S
LS
Gate
Driver • 94
37
Zero-Cycle
Test
Documentation
61
86
LS
Sense
Amplifier
94
38
One-Cycle
Test
Documentation
(Scopex)
62
87
LS
Read
Driver.
94
39
One-Cycle
Test
Scope
Timings
62
88
Module
Side
of
S801S1S
Card
9S
40
Sensitive
Net
Examples
62
ROS
Waveforms
97
89
41
Interface
Register
and Functions
64
ROS Drive Line Tests
98
90
42
Multiplexor
Channel
Progressive Scan Run and
91
ROS
Select
Line Tests
99
Repair
Procedure
6S
ROS Strobe
and
Sense Latch
Test
Points
99
92
43
Selector
Channel
Progressive
Scan
Run
and
93
ROS Sense
Amplifier
and Latch
Card
Locations
99
Repair
Procedures
(3
Parts) •
66
Setscrew
Torque
Sequence
(ROS Bit Planes) 100
94
44
Test
Series 110. 1
Test
01
(Diagnose
Section--Start
I/O
Write Series) •
69
9S
SP
Reference
Voltage
Tracking
102
4S
Typical
Test
Series (Series 110)
69
96
SP
Inhibit
Driver
and Sense Amp Locations •
102
46
Scan
Test
Timing
Procedure
69
97
SP
Sense Winding
Test
Points 103
47
Start
liO
Write
Timing
70
98
Storage
Protect
Driver Locations 103
48
Selector
Channel
A
Clock:
Signal
Sequences
72
99
Selector
Channel
Maintenance
Approach
lOS
49
Progressive
Scan
Printout
(Sel
Ch).
73
100
Reset
Pulses
(Clock
Not Running) 107
vi
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