(b)
PLL LOOP CIRCUIT
The
VCO
output
is amplified by IC10 and passes
through a LPF,
02
and is multiplied by
two
at a
doubler
circuit
consisting
of
01,
02
and
L5.
It is
fed
to
the BPF, and then is applied
to
the MAIN UNIT
as a
1st
LO
signal.
A part
of
the
VCO
output
signals (Fvco) is amplified
by
IC5, and is mixed with the
LO
signal in the PLL
loop (Fa) from the
VCO
UNIT
at
IC6 for heterodyning.
The relation
of
Fb, Fvco and Fa is as
follows:
Fb=Fvco-Fa
(See Fig.
7)
The signal from IC6 (Fb) passes through
L9,
L 10,
and
01,
and
it
is fed
to
IC4. The
limiter
05
and
06
prevents excessive signal input.
(c)
LO
CIRCUIT IN PLL LOOP
When
FRx
is between
25
and 249.9999MHz or
512
and 761.9999MHz:
The
output
of
X2
(51.2MHz) is multiplied by three at
010. The signal from
010
passes through
L18~L20,
and -011, and then
it
is multiplied by
two
at
012
to
obtain Fe (307.2MHz). The
output
of
012
passes
through
L23
and
L25
and then is fed
to
mixer IC8.
When
FRx
is between 250 and 511.9999MHz
or
762
and 999.9999MHz:
The
output
of
X2
(51.2MHz) is multiplied by four at
016. The signal from
016
passes through
L31~L33,
and
017
and then is
multiplied
by two at
018
to
obtain Fe (409.6MHz). The
output
of
018
passes
through
L36
and
L38
and then is fed
to
mixer IC8.
X1
oscillates 12MHz band signals, and the
DA
signal
from the LOGIC UNIT controls
oscillation
frequencies
of
X1.
Signals from
X1
are multiplied by three
at
015
to
obtain Fd.
Fd varies between
36
and 36.00495MHz in 50Hz
steps.
In
addition, Fd
shifts
±0.75kHz
depending
on the
[USB/LSB] SELECTOR SWITCH. The
output
of
the
1st
LO
signal
(F1s1Lo)
is obtained by double
multiplication, so F
1
stLO
shifts
±1.5kHz.
Fd and Fe are mixed
at
IC8
to
obtain Fa (the
LO
frequency in the PLL loop). The relation
of
Fa, Fe
and Fd is as
follows:
Fa=Fc+Fd
(See Fig.
7)
4-4
LOGIC CIRCUIT (LOGIC UNIT)
4·4·1
CPU
IC?
(a
high-speed 8-bit COMS
CPU)
controls data such
as mode, receive band,
VCOs and expanded
output
ports IC9 and IC10.
The CPU's port addressing is shown in Fig.
9.
4-8
GND
CRYSTAL
CRYSTAL
WR
NC
RXD (Cl-V)
TXD (Cl-V)
SS1
A5
A4
cs
PROG
RES
CTL
CPU PIN
CONNECTION
Fig. 8
4·4·2 MATRIX ALLOCATION
DBO
DB1
DATA
DB2 BUS
DB3
DB4
DB5
DB6
DB?
Y1/A9
Y2/A8
Y3/A7
Y4/A6
Y5/A3
Y6/A2
A1
AO
5V
The matrix allocation is shown in Fig.
10.
Y1
Y2
Y3
KEYBOARD
[TS]
Y4
Y5
Y6
Cl-V
ADDRESS
Cl-V
TRANSCEIVE
~--!+--..>..j~-+-...>....~-+---"--~++---"--t---t-->-~-+-.>.~DB5
Cl-V
[VSC] BAUD RATE
(MAIN
UNIT]
Fig. 9
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